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參數(shù)資料
型號: U62H256SK35
英文描述: Low power JFET dual operational amplifiers
中文描述: x8的SRAM
文件頁數(shù): 2/9頁
文件大?。?/td> 123K
代理商: U62H256SK35
2
March 8, 1999
U62H256S
*H or L
Characteristics
All voltages are referenced to V
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
= 0 V and V
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
Truth Table
Block Diagram
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.5
V
CC
+ 0.5
V
Output Voltage
V
O
-0.5
V
CC
+ 0.5
V
Power Dissipation
P
D
-
1
W
Operating Temperature
K-Type
A-Type
T
a
-40
-40
85
125
°
C
Storage Temperature
T
stg
-65
150
°
C
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
**
**
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
| I
OS
|
200
mA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
CC
V
SS
W
G
E
R
I
C
I
Address
Change
Detector
C
R
Sense Amplifier/
Write Control Logic
Clock
Generator
C
Memory Cell
Array
256 Rows x
128 x 8 Columns
A0
A1
A2
A3
A10
A5
A6
A7
A8
A9
A4
A11
A12
A13
A14
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