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參數資料
| 型號： | U62H824PC35 |
| 英文描述： | Low power JFET quad operational amplifier |
| 中文描述： | x24的SRAM |
| 文件頁數： | 2/10頁 |
| 文件大小： | 87K |
| 代理商： | U62H824PC35 |
U62H824
November 01, 2001
2
Block Diagram
DQ23
DQ0
G
W
E2
E1
&
&
&
1
0
(LSB)
(MSB)
Input Data
Control
2 to 1 MUX
V/S
Q
Row
Decoder
Memory Cell
Array
256 Rows x
768 Columns
V
CC
V
SS
Column I/O
Column Decoder
A12i
X/Y
A12
A0
A5
A10
A11
A6
A9
Mode
E1
E2
G
W
V/S
Supply
Current
I/O
Status
Not Selected
H
X
X
X
X
I
CC(SB)
High - Z
Not Selected
X
L
X
X
X
I
CC(SB)
High - Z
Output Disable
L
H
H
H
X
I
CC(OP)
High - Z
Read Using X/Y
L
H
L
H
H
I
CC(OP)
Data Out
Read Using A12
L
H
L
H
L
I
CC(OP)
Data Out
Write Using X/Y
L
H
X
L
H
I
CC(OP)
Data In
Write Using A12
L
H
X
L
L
I
CC(OP)
Data In
Truth Table
Characteristics
All voltages are referenced to V
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
= 0 V and V
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Input Low Voltage *
V
IL
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
*
-2 V at Pulse Width
≤
10 ns
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相關代理商/技術參數 |
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