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參數資料
| 型號： | UCB1400BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Audio codec with touch screen controller and power management monitor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, PLASTIC, LQFP-48 |
| 文件頁數： | 8/63頁 |
| 文件大小： | 674K |
| 代理商： | UCB1400BE |
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Philips Semiconductors
UCB1400
Audio codec with touch screen controller
and power management monitor
Product data
Rev. 02 — 21 June 2002
8 of 63
9397 750 09611
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
8.3.2
AC-link audio output frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all
digital output data targeting UCB1400’s DAC inputs, and control registers. Each audio
output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special
reserved time slot containing 16 bits which are used for AC-link protocol
infrastructure.
Slot 0: TAG:
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which
flags the validity for the entire audio frame. If the ‘Valid Frame’ bit is a 1, this indicates
that the current audio frame contains at least one slot time of valid data. The next 12
bit positions sampled by UCB1400 indicate which of the corresponding 12 time slots
contain valid data. In this way, data streams of differing sample rates can be
transmitted across AC-link at its fixed 48 kHz audio frame rate.
Figure 6
illustrates the time slot based AC-link protocol. (Note that Bits 1 and 0 of
slot 0 tag phase are used for primary/secondary codec addressing as described in
Section 8.4
.
A new audio output frame begins with a LOW-to-HIGH transition of SYNC. SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the UCB1400 samples the assertion of SYNC. This falling edge marks
the time when both sides of AC-link are aware of the start of a new audio frame. On
the next rising of BIT_CLK, the AC ’97 Controller transitions SDATA_OUT into the first
bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on
a rising edge of BIT_CLK, and subsequently sampled by UCB1400 on the following
falling edge of BIT_CLK. This sequence ensures that data transitions, and
subsequent sample points for both incoming and outgoing data streams are time
aligned.
* See
Table 4
.
Fig 6.
AC Link audio output frame.
20.8
μ
s
(48 kHz)
TAG PHASE
DATA PHASE
81.4 ns
(12.288 MHz)
VALID
FRAME
SYNC
BIT_CLK
SDATA_OUT
END OF PREVIOUS
AUDIO FRAME
slot(1)
slot(2)
slot(12)
“0”
*
*
19
0
19
0
19
0
19
0
TIME SLOT “VALID” BITS
(“1” = TIME SLOT CONTAINS VALID PCM DATA)
SLOT 1
SLOT 2
SLOT 3
SLOT 12
SN00221
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UCB1400BE,128 | 功能描述:接口—CODEC AUDIO CODEC WITH TOUCHSCREEN RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UCB1400BE,151 | 功能描述:接口—CODEC AUDIO CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UCB1400BE,157 | 功能描述:接口—CODEC DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UCB1400BEFE | 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數據接口:串行 分辨率（位）:18 b ADC / DAC 數量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| UCB1400BE-S | 功能描述:接口—CODEC AUDIO CODEC NO NEW DESIGNS RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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