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參數(shù)資料
| 型號： | UDA1309H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Low-power stereo bitstream ADC/DAC(低功耗立體聲位流ADC/DAC) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 150K |
| 代理商： | UDA1309H |
1998 Jan 06
15
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
Notes
1.
V
I
for full scale digital output is a function of V
DDA(AD)
[1.0 V (RMS) at V
DDA(AD)
= 5.0 V is equivalent to
1.0 dB in the
digital domain].
V
ripple
= 1% of the supply voltage and f
ripple
= 100 Hz.
At full scale digital input; no de-emphasis; V
O(rms)
is a function of V
DDA(DA)
.
For a load capacitance greater than 33 pF a series resistor of 200
is recommended.
18 bits input data.
The aliasing suppression frequency is mirrored around 128f
s
.
V
DDA
= 5 V; indicated digital level is with respect to
1.0 dB (no overload).
All digital voltages = 4.5 to 5.5 V; all ground supply voltages = 0 V; T
amb
=
20 to +75
°
C.
2.
3.
4.
5.
6.
7.
8.
Timing
B
IT CLOCK
(BCK)
RELATED SIGNALS
(see Fig.6); CLKEDGE = 0
T
cy
t
HC
t
LC
t
r
t
f
t
suWS
clock period
clock HIGH time
clock LOW time
rise time
fall time
set-up time WS to rising
edge of BCK
hold time WS to rising edge
of BCK
set-up time SDA (DAC) to
rising edge of BCK
hold time SDA (DAC) to
rising edge of BCK
hold time SDA (ADC) to
falling edge of BCK
delay time SDA (ADC) to
falling edge of BCK
300
100
100
20
20
20
ns
ns
ns
ns
ns
ns
t
hWS
0
ns
t
suDA
20
ns
t
hDA
0
ns
t
hAD
0
ns
t
dAD
80
ns
S
YSTEM CLOCK
(SYSCLK)
RELATED SIGNALS
(see Fig.7)
T
cy
t
HC
t
LC
t
r
t
f
clock period
clock HIGH time
clock LOW time
rise time
fall time
72
22
22
10
10
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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