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參數(shù)資料
| 型號： | UDA1309H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Low-power stereo bitstream ADC/DAC(低功耗立體聲位流ADC/DAC) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 150K |
| 代理商： | UDA1309H |
1998 Jan 06
7
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
FUNCTIONAL DESCRIPTION
Figure 1 illustrates the various components of the
UDA1309H.
The analog-to-digital converter is a bitstream type
converter, both channels are sampled simultaneously.
The digital-to-analog converter is a BCC (Bitstream
Continuous Calibration) type converter. The digital filter for
the ADC is a bit serial IIR filter that produces a fairly linear
phase response up to 15 kHz. A high-pass filter is
incorporated in the down-sampling path to remove DC
offsets. An overload detection circuit is incorporated to
facilitate automatic recording level adjustment.
The digital up-sample filter for the DAC is partly IIR, with
virtual linear phase response up to 15 kHz, and partly FIR.
A switchable digital de-emphasis circuit is also
incorporated. Due to the BCC principle used, the DAC
needs only single pole post-filtering (one external
capacitor) to meet the out-of-band suppression
requirement.
The ADC and DAC channels have separate power-down
modes, to reduce power if one of them is not in use.
An analog loop-through function enables analog-input
analog-output mode without using the ADC and DAC
converters or filters, thereby switching them off to reduce
power consumption.
The digital interfaces accommodates, 16 and 18-bit,
I
2
S-bus and LSB justified formats. The ADC digital output
can be made 3-state by means of the ADENB signal, this
enables the use of a digital bus.
The UDA1309H interface accommodates slave mode
only, therefore, the system ICs must provide the system
clock, bit clock and word clock signals. For the DAC, the
UDA1309H accepts the data together with these clocks,
for the ADC it delivers the data in response to these clocks.
Within one stereo frame, the first sample always
represents the left channel. When sending data the
unused bit positions are set to zero, when receiving data
these bit positions are don't cares.
To accommodate the various interface formats and
system clock frequencies four control pins are provided,
MODE0 to MODE2 for mode selection and CLKEDGE
which selects the active edge of the BCK signal. Table 1
gives the interface mode selection, Fig.3 illustrates the
ADC/DAC data formats and Fig.5 the operating modes.
The section of the UDA1309H is designed to
accommodate two main modes:
1.
The 256f
s
mode in which analog-to-digital and
digital-to-analog can be used.
2.
The 192f
s
or 384f
s
mode (digital-to-analog only).
Table 1
Interface mode selection
Note
1.
Only digital-to-analog.
Table 2
Clock edge mode
DEVICE PIN
ADC/DAC FORMATS
MODE 2
MODE 1
MODE 0
TYPE
BITS
BCK
SYS; f
sys
256f
s
256f
s
192f
s(1)
256f
s
256f
s
256f
s
384f
s(1)
256f
s
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LSB justified
LSB justified
LSB justified
LSB justified
I
2
S-bus
I
2
S-bus
I
2
S-bus
I
2
S-bus
16
16
16
18
16
16
16
18
32f
s
64f
s
48f
s
64f
s
32f
s
64f
s
48f
s
64f
s
3(a)
3(b)
4(a)
3(c)
3(d)
3(e)
4(b)
3(f)
CLKEDGE
VALID EDGE OF BCK
ADC
DAC
0
1
falling
rising
rising
falling
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