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參數(shù)資料
| 型號： | UDA1324TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Ultra low-voltage stereo filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 107K |
| 代理商： | UDA1324TS |
2000 Jan 20
10
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
S
YSTEM CLOCK FREQUENCY
The system clock frequency is a 2-bit value to select the
external clock frequency.
Table 8
System clock settings
D
ATA FORMAT
The data format is a 3-bit value to select the used data
format.
Table 9
Data input format settings
D
E
-
EMPHASIS
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 10
De-emphasis settings
V
OLUME CONTROL
The volume control is a 6-bit value to program the volume
attenuation from 0 to
60 dB and
∞
dB in steps of 1 dB.
Table 11
Volume settings
M
UTE
Mute is a 1-bit value to enable the digital mute.
Table 12
Mute setting
SC1
SC0
FUNCTION
0
0
1
1
0
1
0
1
512f
s
384f
s
256f
s
not used
IF2
IF1
IF0
FORMAT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I
2
S-bus
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
MSB-justified
not used
not used
not used
DE1
0
0
1
1
DE0
0
1
0
1
FUNCTION
no de-emphasis
de-emphasis, 32 kHz
de-emphasis, 44.1 kHz
de-emphasis, 48 kHz
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
0
0
0
0
:
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
:
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
:
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
:
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
:
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
:
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
2
:
51
52
54
57
60
∞
MT
FUNCTION
0
1
no muting
muting
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