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參數資料
| 型號： | UDA1324TS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Ultra low-voltage stereo filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數： | 12/20頁 |
| 文件大?。?/td> | 107K |
| 代理商： | UDA1324TS |
2000 Jan 20
12
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
Notes
1.
2.
All supply connections must be made to the same external power supply unit.
When the DAC drives a capacitive load above 50 pF, a series resistance of 100
must be used to prevent
oscillations in the output operational amplifier.
AC CHARACTERISTICS
V
DDD
= V
DDA
= 2.0 V; f
i
= 1 kHz; T
amb
= 25
°
C; R
L
= 5 k
; all voltages referenced to ground (pins V
SSA
and V
SSD
);
unless otherwise specified.
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3
V
IH
V
IL
I
LI
C
I
Three-level input: pin APPSEL
HIGH-level input voltage
LOW-level input voltage
input leakage current
input capacitance
0.8V
DDD
0.2V
DDD
1
10
V
V
μ
A
pF
V
IH
V
IM
V
IL
DAC
HIGH-level input voltage
MIDDLE-level input voltage
LOW-level input voltage
0.8V
DDD
0.3V
DDD
0.5
V
DDD
+ 0.5 V
0.7V
DDD
0.2V
DDD
V
V
V
ref(DAC)
I
o(max)
reference voltage
maximum output current
referenced to V
SSA
(THD + N)/S < 0.1%;
R
L
= 5 k
0.45V
DDA
0.5V
DDA
0.16
0.55V
DDA
V
mA
R
O
R
L
C
L
output resistance
load resistance
load capacitance
3
0.15
2.0
50
k
pF
note 2
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DAC
V
o(rms)
V
o
output voltage (RMS value)
unbalance voltage between
channels
total harmonic
distortion-plus-noise to
signal ratio
signal-to-noise ratio
channel separation
power supply ripple rejection
ratio
500
0.1
mV
dB
(THD + N)/S
at 0 dB
at
60 dB; A-weighted
83
36
78
dB
dB
S/N
α
cs
PSRR
code = 0; A-weighted
97
100
50
dB
dB
dB
f
ripple
= 1 kHz;
V
ripple
= 100 mV (p-p)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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