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參數資料
| 型號： | UDA1325 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Universal Serial Bus USB CODEC |
| 中文描述： | 通用串行總線解碼器 |
| 文件頁數： | 28/52頁 |
| 文件大小： | 310K |
| 代理商： | UDA1325 |
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1999 May 10
28
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 23
ASR control register
START-UP BEHAVIOUR AND POWER MANAGEMENT
Start-up of the UDA1325
After power-on (of V
DDA1
), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is
created by using the internal resistor (2
×
50 k
) divider for creating the reference voltage for the FSDAC in combination
with the capacitor connected externally to the V
REFDA
pin. The FSDAC and the internal resistor divider are supplied by
V
DDA1
and V
SSA1
. The RC time can be calculated using R = 25000
and C = C
ref
.
During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this
initialisation, the user should prevent indicating the ‘connected’ status to the USB-host. This can be done by forcing the
DP-line LOW (i.e. via one of the GP pins).
Power Management
The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less
than 500
μ
A in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can
be reduced by disabling all internal clocks and switching off all internal analog modules.
Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a
number of precautions must be taken!
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
2000h
ASR control register
robust word clock
7
0 = off (not recommended)
1 = on (recommended)
00 = I
2
S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
0 = mono phase inversal off
1 = mono phase inversal on
00 = reserved
01 = 8-bit audio
10 = 16-bit audio
11 = 24-bit audio
0 = mono
1 = stereo
0 = stop (e.g. at alternate
setting with bandwidth equal to
zero)
1 = go
serial I
2
S-bus output format
digital I/O interface
6 and 5
phase inversion (on right mono
output)
4
bits per sample modi
3 and 2
mono or stereo operation
1
ASR register start-up mode
0
相關PDF資料 |
PDF描述 |
|---|---|
| UDA1325H | Universal Serial Bus USB CODEC |
| UDA1325PS | Universal Serial Bus USB CODEC |
| UDA1326PS | USB AUDIO-CODEC(通用串行總線音頻編解碼器) |
| UDA1331H | Universal Serial Bus USB Audio Playback Peripheral APP |
| UDA1334BT | Low power audio DAC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1325H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus USB CODEC |
| UDA1325PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus USB CODEC |
| UDA1328 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multi-channel filter DAC |
| UDA1328T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multi-channel filter DAC |
| UDA1330A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-cost stereo filter DAC |
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