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參數(shù)資料
| 型號： | UDA1350ATS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | IEC 958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 124K |
| 代理商： | UDA1350ATS |
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2000 Mar 29
11
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350ATS
8.5.2
L3
CONTROL MODE
The L3 control mode allows maximum flexibility in controlling the UDA1350ATS.
It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and
that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface.
Table 4
Pin description in the L3 control mode
PIN
NAME
VALUE
FUNCTION
Mode selection pin
26
SELSTATIC
0
select L3 control mode; must be connected to V
SSD
Input pins
5
RESET
0
1
normal operation
reset
must be connected to the L3-bus
must be connected to the L3-bus
must be connected to the L3-bus
8
9
10
L3DATA
L3CLOCK
L3MODE
Status pins
16
LOCK
0
1
clock regeneration and IEC 958 decoder out-of-lock
or
non-PCM data detected
clock regeneration and IEC 958 decoder locked
and
PCM data detected
Test pins
4
TEST1
TEST2
TEST4
TEST3
0
0
1
0
must be connected to ground (V
SSD
)
must be connected to ground (V
SSD
)
must be connected to digital supply voltage (V
DDD
)
must be connected to ground (V
SSD
)
18
25
28
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