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參數(shù)資料
| 型號： | UDA1350ATS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | IEC 958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 124K |
| 代理商： | UDA1350ATS |
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2000 Mar 29
18
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350ATS
8.6.8.7
Soft mute
A 1-bit value to enable the digital mute.
Table 15
Soft mute selection
8.6.8.8
Volume control
A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to
∞
dB in steps of 1 dB.
Table 16
Volume settings of the interpolator
8.6.8.9
Auto mute
A 1-bit value to activate mute during out-of-lock. In normal
operation the output is automatically hard muted when an
out-of-lock situation is detected. Setting this bit to logic 0
will disable that function.
Table 17
Auto mute setting
8.6.8.10
PLL reset
A 1-bit value to reset the PLL. This is the bit which is set in
the initialisation string. When this bit is asserted, the PLL
will be reset and the output clock of the PLL will be forced
to its lowest value, which is in the area of a few MHz.
Table 18
PLL reset
MT
FUNCTION
0
1
no muting
muting (default setting)
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME
(dB)
0
0
0
0
:
1
1
1
1
1
0
0
0
0
:
1
1
1
1
1
0
0
0
0
:
1
1
1
1
1
0
0
0
0
:
0
1
1
1
1
0
0
1
1
:
1
0
0
1
1
0
1
0
1
:
1
0
1
0
1
0
0
1
2
:
58
59
60
∞
∞
Auto MT
FUNCTION
0
1
do not mute output during out-of-lock
mute output during out-of-lock (default
setting)
RST PLL
FUNCTION
0
1
normal operation
PLL is reset
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