
Direct Rambus Clock Generator
W134M/W134S
Cypress Semiconductor Corporation
Document #: 38-07426 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Differential clock source for Direct Rambus
memory
subsystem for up to 800-MHz data transfer rate
Provide synchronization flexibility: the Rambus
Chan-
nel can optionally be synchronous to an external sys-
tem or processor clock
Power managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
Works with Cypress CY2210, W133, W158, W159, W161,
and W167 to support Intel
architecture platforms
Low-power CMOS design packaged in a 24-pin, 150-mil
SSOP package
Overview
The Cypress W134M/W134S provides the differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
Key Specifications
Supply Voltage: ..................................... V
DD
= 3.3V±0.165V
Operating Temperature: .................................. 0
°
C to +70
°
C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:.........................................V
DD
+0.5V
Maximum Input Frequency:.....................................100 MHz
Output Duty Cycle: .................................. 40/60% worst case
Output Type:........................... Rambus signaling level (RSL)
Block Diagram
Pin Configuration
PLL
Phase
Alignment
PCLKM
MULT0:1
REFCLK
SYNCLKN
Output
Logic
Logic
Test
STOPB
S0:1
CLK
CLKB
S0
S1
VDD
GND
CLK
NC
CLKB
GND
VDD
MULT0
MULT1
GND
24
23
22
21
20
19
18
17
16
15
14
13
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12