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參數資料
| 型號： | W183G |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|CMOS|SOP|14PIN|PLASTIC |
| 中文描述： | 雜項時鐘發生器|的CMOS |專科| 14PIN |塑料 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 124K |
| 代理商： | W183G |
Full Feature Peak Reducing EMI Solution
W183
Cypress Semiconductor Corporation
Document #: 38-07158 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 25, 2001
408-943-2600
Features
Cypress PREMIS
family offering
Generates an EMI optimized clocking signal at the out-
put
Selectable output frequency range
Single 1.25%, 3.75% down or center spread output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages:...........................................V
DD
= 3.3V±5%
or V
DD
= 5V±10%
Frequency Range: ............................ 28 MHz
≤
F
in
≤
75 MHz
Crystal Reference Range:................. 28 MHz
≤
F
in
≤
40 MHz
Cycle to Cycle Jitter: .......................................300 ps (max.)
Selectable Spread Percentage:....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: ..................................5 ns (max.)
Table 1. Modulation Width Selection
SS%
W183
Output
W183-5
Output
0
F
in
≥
F
out
≥
F
in
–
1.25%
F
in
+ 0.625%
≥
F
in
≥
–
0.625%
1
F
in
≥
F
out
≥
F
in
–
3.75%
F
in
+ 1.875%
≥
F
in
≥
–
1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
0
0
28 MHz
≤
F
IN
≤
38 MHz
38 MHz
≤
F
IN
≤
48 MHz
46 MHz
≤
F
IN
≤
60 MHz
58 MHz
≤
F
IN
≤
75 MHz
0
1
1
0
1
1
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
SOIC
W
14
13
12
11
10
1
2
3
4
5
6
7
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
REFOUT
OE#
SSON#
Reset
VDD
VDD
CLKOUT
8
9
Spread Spectrum
Output
W183
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
Output
W183
(EMI suppressed)
3.3V or 5.0V
XTAL
Input
X1
X2
40 MHz
Max
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