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參數資料
| 型號： | W204 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 177K |
| 代理商： | W204 |
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
W204
PRELIMINARY
Cypress Semiconductor Corporation
Document #: 38-07264 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 22, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s spread
spectrum technology
Optimized system frequency synthesizer for 440BX and
VIA Apollo Pro-133
Four copies of CPU output
Eight copies of PCI clock (synchronous w/CPU output)
Two copies of 14.318-MHz IOAPIC output and three
buffered copies of 14.318-MHz reference input
One copy of 48-MHz USB output
Selectable 24-/48-MHz clock-through-resistor
strapping
Power management control input pins
Programmable clock outputs up to 155 MHz via SMBus
interface (32 selectable frequencies)
Key Specifications
Supply Voltages:.....................................
VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: ..........................................250 ps
CPU0:3 Output Skew: ................................................175 ps
PCI_F, PCI1:7 Output Skew:.......................................500 ps
CPU to PCI Output Skew: ...............1.0
–
4.0 ns (CPU Leads)
REF0/SEL48#, SCLK,SDATA:........................... 250K pull-up
FS1:...............................................................250K pull-down
FS0:...................................................No pull-up or pull-down
Test mode and output three-state through SMBus interface
Table 1. Pin Selectable Frequency
FS1
1
1
0
0
FS0
1
0
1
0
CPU(0:3)
133.3 MHz
105 MHz
100 MHz
66.8 MHz
PCI
33.3 MHz
35 MHz
33.3 MHz
33.3 MHz
Pin Configuration
Block Diagram
VDDQ3
REF0/SEL48#
VDDQ2
APIC0
CPU0
CPU1
GND
VDDQ2
CPU2
CPU3
GND
PCI_F
XTAL
OSC
PLL Ref Freq
PLL 1
FS0:1
X2
X1
REF1
VDDQ3
Stop
Stop
Clock
Control
PCI1
PWR_DWN#
Power
Down
Control
PCI2
PCI3
GND
PCI4
PCI5
PCI6
48MHz
24_48MHz/FS1
GND
PLL2
÷
2/
÷
3
REF2
GND
VDDQ2
PCI_STOP#
CPU_STOP#
PCI7
GND
VDDQ3
APIC1
GND
GNDCORE0/1
VDDCORE0/1
VDDQ3
SPREAD#
I
2
C
Logic
SDATA
SCLK
REF0/SEL48#
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
24_48MHz/FS1
GND
VDDQ3
REF2
VDDQ2
APIC0
APIC1
GND
NC
VDDQ2
CPU0
CPU1
GND
VDDQ2
CPU2
CPU3
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SDATA
SCLK
FS0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
[1]
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