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參數資料
| 型號： | W256 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 12 Output Buffer for 2 DDR and 3 SRAM DIMMS |
| 中文描述： | LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, SSOP-28 |
| 文件頁數： | 4/9頁 |
| 文件大?。?/td> | 176K |
| 代理商： | W256 |
W256
Document #: 38-07256 Rev. *C
Page 4 of 9
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............–0.5V to V
DD
+0.5
Storage Temperature ..................................–65°C to +150°C
Static Discharge Voltage............................................>2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[2]
Parameter
V
DD3.3
V
DD2.5
T
A
C
OUT
C
IN
Description
Min.
3.135
2.375
0
Typ.
Max.
3.465
2.625
70
Unit
V
V
°C
pF
pF
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
6
5
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
IH
I
IL
I
IH
I
OH
Description
Test Conditions
For all pins except SMBus
Min.
Typ.
Max.
0.8
Unit
V
V
μ
A
μ
A
mA
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
2.0
V
IN
= 0V
V
IN
= V
DD
V
DD
= 2.375V
V
OUT
= 1V
V
DD
= 2.375V
V
OUT
= 1.2V
I
OL
= 12 mA, V
DD
= 2.375V
I
OH
= –12 mA, V
DD
= 2.375V
Unloaded outputs, 133 MHz
50
50
–18
–32
I
OL
Output LOW Current
26
35
mA
V
OL
V
OH
I
DD
Output LOW Voltage
[3]
Output HIGH Voltage
[3]
Supply Current
[3]
(DDR-Only mode)
Supply Current
(DDR-Only mode)
Supply Current
Output Voltage Swing
0.6
V
V
1.7
400
mA
I
DD
Loaded outputs, 133 MHz
500
mA
I
DDS
V
OUT
PWR_DWN# = 0
See Test Circuity (Refer to
Figure 1
)
100
μ
A
V
0.7
V
DD
+ 0.6
V
OC
Output Crossing Voltage
(V
DD
/2)
–0.1
48
V
DD
/2
(V
DD
/2)
+0.1
52
V
IN
DC
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Input Clock Duty Cycle
%
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