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參數資料
| 型號： | W25P025A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K×32 Burst Pipeline High-Speed CMOS Static RAM(64K×32位同步脈沖管線高速CMOS靜態RAM) |
| 中文描述： | 64K的管道爆裂× 32高速CMOS靜態RAM（64K的× 32位同步脈沖管線高速的CMOS靜態RAM）的 |
| 文件頁數： | 11/17頁 |
| 文件大小： | 313K |
| 代理商： | W25P025A |
W25P025A
Publication Release Date: January 1998
- 11 -
Revision A3
Timing Waveforms, continued
Write Cycle Timing
1a
Single Write
Burst Write
Unselected
T
CYC
CLK
T
ADSS
T
ADSH
T
KH
T
KL
ADSP is blocked by CE1 inactive
T
ADCS
T
ADCH
ADSC initiated write
T
ADVS
T
ADVH
T
AS
T
AH
WR1
WR2
WR3
T
WS
T
WH
T
WS
T
WH
T
CES
T
CEH
CE1 masks ADSP
T
CES
T
CEH
T
CES
T
CEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[4:1]
CE1
CE2
CE3
OE
Data-Out
Data-In
2a
2b
2c
2d
3a
Write
GWE allows processor address (and BE=BW)
to be pipelined during a writeback
T
WS
T
WH
WR1
WR2
WR3
T
DS
T
DH
BW[4:1] are applied only to first cycle of WR2
ADV must be inactive for ADSP write
DON'T CARE
UNDEFINED
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