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參數資料
| 型號： | W25P025A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K×32 Burst Pipeline High-Speed CMOS Static RAM(64K×32位同步脈沖管線高速CMOS靜態RAM) |
| 中文描述： | 64K的管道爆裂× 32高速CMOS靜態RAM（64K的× 32位同步脈沖管線高速的CMOS靜態RAM）的 |
| 文件頁數： | 9/17頁 |
| 文件大小： | 313K |
| 代理商： | W25P025A |
W25P025A
Publication Release Date: January 1998
- 9 -
Revision A3
AC Timing Characteristics, continued
PARAMETER
SYM.
W25P025AX-6/
W25P025AX-6F
W25P025AX-7/
W25P025AX-7F
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
ADV
Setup Time
T
ADVS
2.5
-
2.5
-
nS
ADV
Hold Time
T
ADVH
0.5
-
0.5
-
nS
ADSP
Setup Time
T
ADSS
2.5
-
2.5
-
nS
ADSP
Hold Time
T
ADSH
0.5
-
0.5
-
nS
ADSC
Setup Time
T
ADCS
2.5
-
2.5
-
nS
ADSC
Hold Time
T
ADCH
0.5
-
0.5
-
nS
CE1
, CE2,
CE3
Setup Time
T
CES
2.5
-
2.5
-
nS
CE1
, CE2,
CE3
Hold Time
T
CEH
0.5
-
0.5
-
nS
GW
,
BWE
X Setup Time
T
WS
2.5
-
2.5
-
nS
GW
,
BWE
X Hold Time
T
WH
0.5
-
0.5
-
nS
Clock Cycle Time
T
CYC
13.3
-
15
-
nS
Clock High Pulse Width
T
KH
5
-
6 / 5.5
-
nS
1
Clock Low Pulse Width
T
KL
5
-
6 / 5.5
-
nS
1
Clock to Output Valid
T
KQ
-
6
-
7
nS
Clock to Output High-Z
T
KHZ
2
13.3
2
15
nS
2
Clock to Output Low-Z
T
KLZ
0
-
0
-
nS
2
Clock to Output Invalid
T
KX
2
-
2
-
nS
2
Output Enable to Output Valid
T
OE
-
6
-
7
nS
Output Disable to Output High-Z
T
OHZ
-
6 / 4
-
7 / 5
nS
1,2
Output Enable to Output Low-Z
T
OLZ
0
-
0
-
nS
2
Output Disable to Output Invalid
T
OX
0
-
0
-
nS
ZZ Standby Time
T
ZZS
-
100 / 80
-
100 / 80
nS
1,3
ZZ Recover Time
T
ZZR
100 / 80
-
100 / 80
-
nS
1,4
Notes:
1. The discriminator "/" separate the different values for W25P025AX-n and W25P025AX-nF individually. For example, the T
KH
is
6 nS and 5.5 nS for W25P025AX-n and W25P025AX-nF individually.
2. These parameters are sampled but not 100% tested.
3. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
4. ADSC and ADSP should not be accessed for at least 100 nS / 80nS after chip leaves ZZ mode.
5. Configuration signals LBO and FT are static and should not be changed during operation.
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