- 您現在的位置：買賣IC網 > PDF目錄363874 > W25P240AF-6A (WINBOND ELECTRONICS CORP) x64 Fast Synchronous SRAM PDF資料下載
參數資料
| 型號： | W25P240AF-6A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | x64 Fast Synchronous SRAM |
| 中文描述： | 64K X 64 STANDARD SRAM, 7 ns, PQFP100 |
| 封裝： | MO-108, QFP-100 |
| 文件頁數： | 3/14頁 |
| 文件大小： | 166K |
| 代理商： | W25P240AF-6A |
W25P240A
Publication Release Date: February 1998
- 3 -
Revision A4
PIN DESCRIPTION
SYMBOL
A0
A15
I/O1
I/O64
CLK
TYPE
DESCRIPTION
Input, Synchronous
I/O, Synchronous
Input, Clock
Input, Synchronous
Host Address
Data Inputs/Outputs
Processor Host Bus Clock
Chip Enables
CE
GW
Input, Synchronous
Global Write
BWE
Input, Synchronous
Byte Write Enable from Cache Controller
BW1
BW8
Input, Synchronous
Host Bus Byte Enables used with
BWE
OE
Input, Asynchronous
Output Enable Input
ADV
Input, Synchronous
Internal Burst Address Counter Advance
ADSC
Input, Synchronous
Address Status from chip set
ADSP
V
DD
V
SS
Input, Synchronous
Address Status from CPU
Power Supply
Ground
FUNCTIONAL DESCRIPTION
The W25P240A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports only one burst address sequence for Intel
systems. The burst cycles are
initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low.
Burst Address Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
External Start Address
Second Address
Third Address
Fourth Address
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
相關PDF資料 |
PDF描述 |
|---|---|
| W25P243A | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-4A | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-5 | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-6 | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243AD-4A | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1.2V-vf 150ns 5uA-ir DO-41 5K/REEL-13 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W25P243A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243AD-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
發布緊急采購，3分鐘左右您將得到回復。