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參數資料
型號: W25P240AF-6A
廠商: WINBOND ELECTRONICS CORP
元件分類: SRAM
英文描述: x64 Fast Synchronous SRAM
中文描述: 64K X 64 STANDARD SRAM, 7 ns, PQFP100
封裝: MO-108, QFP-100
文件頁數: 4/14頁
文件大小: 166K
代理商: W25P240AF-6A
W25P240A
- 4 -
TRUTH TABLE
CYCLE
ADDRESS
USED
CE
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
0
X
X
Hi-Z
X
Begin Read
External
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
1
0
0
D-Out
Read
Suspend Read
Current
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
1
1
0
D-Out
Read
Begin Write
Current
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
1
1
X
Hi-Z
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to
the bus clock except for theOE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set up the
SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold
are met.
timings
WRITE TABLE
READ/WRITE FUNCTION
GW
1
1
1
BWE
1
0
0
BW8
X
1
1
BW7
X
1
1
BW6
X
1
1
BW5
X
1
1
BW4
X
1
1
BW3
X
1
1
BW2
X
1
1
BW1
X
1
0
Read
Read
Write byte 1 I/O1
I/O8
Write byte 2 I/O9
I/O16
Write byte 2, byte 1
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
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