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參數(shù)資料
| 型號： | W25P243AF-6 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | DIODE ZENER QUAD COMMON-ANODE 200mW 20Vz 5mA-Izt 0.05 0.1uA-Ir 14 SOT-363 3K/REEL |
| 中文描述： | 64K X 64 STANDARD SRAM, 6 ns, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大小： | 264K |
| 代理商： | W25P243AF-6 |
W25P243A
Publication Release Date: August 1999
- 9 -
Revision A3
AC Timing Characteristics, continued
PARAMETER
SYM. W25P243A-4A
W25P243A-5
W25P243A-6
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
ADSP
Setup Time
T
ADSS
2.0
-
2.0
-
2.0
-
nS
ADSP
Hold Time
T
ADSH
1.0
-
1.0
-
1.0
-
nS
ADSC
Setup Time
T
ADCS
2.0
-
2.0
-
2.0
-
nS
ADSC Hold Time
T
ADCH
1.0
-
1.0
-
1.0
-
nS
CE1, CE2, CE3 Setup Time
T
CES
2.0
-
2.0
-
2.0
-
nS
CE1, CE2, CE3 Hold Time
T
CEH
1.0
-
1.0
-
1.0
-
nS
GW , BWE , BWEx Setup
Time
T
WS
2.0
-
2.0
-
2.0
-
nS
GW
,
BWE
,
BWEx
Hold Time
T
WH
1.0
-
1.0
-
1.0
-
nS
Clock Cycle Time
T
CYC
10
-
12
-
13.3
-
nS
Clock High Pulse Width
T
KH
4
-
5
-
6
-
nS
Clock Low Pulse Width
T
KL
4
-
5
-
6
-
nS
Clock Access Time
T
KQ
-
4.5
-
5
-
6
nS
Clock High to Output High-Z
T
KHZ
1.5
10
1.5
12
1.5
13.3
nS
1
Clock High to Output Low-Z
T
KLZ
0
-
0
-
0
1
nS
1
Output Hold from Clock High
T
KX
1.5
-
1.5
-
1.5
-
nS
1
Output Enable to Output Valid
T
OE
-
4.5
-
5
-
6
nS
Output Disable to Output High-Z
T
OHZ
-
4.5
-
5
-
6
nS
1
Output Enable to Output Low-Z
T
OLZ
0
-
0
-
0
-
nS
1
ZZ Standby Time
T
ZZS
-
100
-
100
-
100
nS
2
ZZ Recover Time
T
ZZR
100
-
100
-
100
-
nS
3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals
LBO
and
FT
are static and should not be changed during operation.
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