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參數(shù)資料
| 型號(hào)： | W25Z040A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128K×36bit Pipeline ZWS(Zero-Wait-State) SRAM(128K×36位無(wú)等待時(shí)間的管線CMOS同步靜態(tài)RAM) |
| 中文描述： | 128K的× 36bit管道ZWS（零等待狀態(tài)）的SRAM（128K的× 36位無(wú)等待時(shí)間的管線的CMOS同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 136K |
| 代理商： | W25Z040A |
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W25Z040A
- 4 -
FUNCTIONAL DESCRIPTION
Read Operation
The address is registered on the rising edge of CLK and the associated output data will be valid after
two cycles later.
Write Operation
During the write operation, the input data follows the address by two cycles later. The new incoming
address and data are transferred into a two-stage write buffer while the residing address which are
received two write cycles earlier are used for actual write operation. Data stored in these two-stage
write data registers are used for first two write cycles following the read or unselected cycle. A
subsequent read which matches the address in either write buffer allows the corresponding buffer
data to be passed directly to output register.
Truth Table
CYCLE
ADDRESS
USED
ZZ
CE1
CE2
CE3
CLKE
ADV/LD
WE
BWx
DATA
NOTES
Unselected
No
0
1
X
X
0
0
X
X
Hi-Z
Unselected
No
0
X
0
X
0
0
X
X
Hi-Z
Unselected
No
0
X
X
1
0
0
X
X
Hi-Z
Begin Read
External
0
0
1
0
0
0
1
X
D-Out
3
Continue Read
Next
0
X
X
X
0
1
X
X
D-Out
3
Begin Write
External
0
0
1
0
0
0
0
0
D-In
Begin Write
/NOP
None
0
0
1
0
0
0
0
1
Hi-Z
4
Continue Write
Next
0
X
X
X
0
1
X
0
D-In
Continue Write
/NOP
Next
0
X
X
X
0
1
X
1
Hi-Z
4
Stall
Current
0
X
X
X
1
X
X
X
-
5
Snooze
None
1
X
X
X
X
X
X
X
Hi-Z
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously
with the bus clock except for theOE pin.
4. NOP can be seen as No Operation.
5. If clock enable sampled high occurs during READ cycle, the bus will remain active (valid data). If clock enable sampled
high occurs during WRITE cycle the bus will remain in high-Z state.
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