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參數(shù)資料
| 型號(hào)： | W25Z040A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128K×36bit Pipeline ZWS(Zero-Wait-State) SRAM(128K×36位無等待時(shí)間的管線CMOS同步靜態(tài)RAM) |
| 中文描述： | 128K的× 36bit管道ZWS（零等待狀態(tài)）的SRAM（128K的× 36位無等待時(shí)間的管線的CMOS同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 136K |
| 代理商： | W25Z040A |
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W25Z040A
Publication Release Date: April 1999
- 9 -
Revision A2
AC TIMING CHARACTERISTICS
(V
DD
/V
DDQ
= 3.3V
±
5%, V
SS
/V
SSQ
= 0V, T
A
= 0 to 70
°
C, all timings measured in pipelined mode)
PARAMETER
SYM.
W25Z040A
-3A
W25Z040A
-4
W25Z040A
-4A
W25Z040A
-5
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock Cycle Time
T
CYC
6.7
-
7.5
-
8.5
-
10.0
-
nS
Clock High Pulse Width
T
KH
2.5
-
3.0
-
3.0
-
3.5
-
nS
Clock Low Pulse Width
T
KL
2.5
-
3.0
-
3.0
-
3.5
-
nS
Input Setup Time
T
S
1.5
-
1.5
-
2.0
-
2.0
-
nS
Input Hold Time
T
H
0.5
-
0.5
-
0.5
-
0.5
-
nS
Clock Access Time
T
KQ
-
3.8
-
4.2
-
4.5
-
5.0
nS
Output Hold from Clock High
T
KX
1.5
-
1.5
-
1.5
-
1.5
-
nS
Clock High to Output Low-Z
T
KLZ
1.5
-
1.5
-
1.5
-
1.5
-
nS
1
Clock High to Output High-Z
T
KHZ
-
3.0
-
3.5
-
3.5
-
3.5
nS
1
Output Enable to Output Valid
T
OE
-
3.8
-
4.2
-
4.5
-
5.0
nS
Output Enable to Output Low-Z
T
OLZ
0
0
0
0
nS
1
Output Disable to Output High-Z
T
OHZ
-
3.0
-
3.5
-
3.5
-
3.5
nS
1
ZZ Standby Time
T
ZZS
-
2
-
2
-
2
-
2
Cycle
ZZ Recover Time
T
ZZR
-
20
-
20
-
20
-
20
nS
4
Notes:
1. These parameters are sampled but not 100% tested.
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. Configuration signals LBO and FT are static and should not be changed during operation.
4. Write cycle should not be given for at least 20 nS while the SRAM is transitioning out of ZZ mode.
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