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參數資料
| 型號： | W986408AH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 2M words x 8 bit x 4 Banks SDRAM(2M字 x 8 位 x 4 組同步動態RAM) |
| 中文描述： | 200萬字× 8位× 4個銀行的SDRAM（200萬字× 8位× 4組同步動態RAM）的 |
| 文件頁數： | 1/45頁 |
| 文件大小： | 1337K |
| 代理商： | W986408AH |
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W986408AH
2M x 8 bit x 4 Banks SDRAM
Revision 1.2 Publication Release Date: May, 1998
- 1 -
Features
3.3V
±
0.3V power supply
Comply to PC100/66 specification
2,097,152 words x 4 banks x 8 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Sequential and Interleave burst
Burst read, single-bit writes operation
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W986408AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks
x 8 bits. Using pipelined architecture, W986408AH delivers a data bandwidth of up to 125M (-8H) bytes per second. To fully
comply to the PC100/66 personal computer industrial standard, W986408AH is sorted into three speed grades: -8H, -8N, and
-10. The -8H is compliant to the PC100/CL2 specification, the -8N is compliant to PC100/CL3 specification, and -10 is
compliant to PC/66 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically
generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at
each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential
burst to maximize its performance. W986408AH is ideal for main memory in high performance applications.
Key Parameters
Symbol
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
I
CC6L
Description
min/max
min
min
min
min
max
max
max
max
-8H
8ns
6ns
20ns
20ns
130mA
210mA
2mA
-
-8N
10ns
6ns
20ns
20ns
130mA
210mA
2mA
-
-10
10ns
8ns
30ns
30ns
110mA
190mA
2mA
-
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current ( Single bank )
Burst Operation Current
Self-Refresh Current
Self-Refresh Current
相關PDF資料 |
PDF描述 |
|---|---|
| W986408BH | 2M words x 8 bit x 4 Banks SDRAM(2M字 x 8 位 x 4 組同步動態RAM) |
| W986408CH | 2M x 8BIT x 4 BANKS SDRAM |
| W986408CH-75 | x8 SDRAM |
| W986408CH-8H | x8 SDRAM |
| W986416AH | 1M words x 16 bit x 4 Banks SDRAM(1M字 x 16 位 x 4 組同步動態RAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W986408CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M x 8BIT x 4 BANKS SDRAM |
| W986408CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W986408CH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W986416CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M x 16 BIT x 4 BANKS SDRAM |
| W986416CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
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