
W986408BH
2M x 8 bit x 4 Banks SDRAM
Revision 1.2 Publication Release Date: April, 1999
- 1 -
Features
3.3V
±
0.3V power supply
Comply to PC133/100/66 specification
2,097,152 words x 4 banks x 8 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Sequential and Interleave burst
Burst read, Single Writes Mode
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W986408BH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x
8 bits. Using pipelined architecture and 0.25um process technology, W986408BH delivers a data bandwidth of up to 133M (-
75) bytes per second. To fully comply to the PC133/100/66 personal computer industrial standard, W986408BH is sorted into
four speed grades: -75, -8H, -8N, and -10. The –75 is compliant to the PC133/CL3 specification, -8H is compliant to the
PC100/CL2 specification, the -8N is compliant to PC100/CL3 specification, and -10 is compliant to PC/66 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986408BH is ideal for main memory in high performance applications.
Key Parameters
Symbol
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
Description
min/max
min
max
min
min
max
max
max
-75
7.5ns
5.4ns
20ns
20ns
90mA
140mA
1mA
-8H
8ns
6ns
20ns
20ns
90mA
140mA
1mA
-8N
10ns
6ns
20ns
20ns
90mA
140mA
1mA
-10
10ns
8ns
30ns
30ns
70mA
110mA
1mA
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current ( Single bank )
Burst Operation Current
Self-Refresh Current