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參數資料
| 型號： | WED8L24514V |
| 英文描述： | Asynchronous SRAM, 3.3V, 512Kx24(512Kx24，3.3V,CMOS異步靜態RAM) |
| 中文描述： | 異步SRAM，3.3伏，512Kx24（512Kx24，3.3，的CMOS異步靜態RAM）的 |
| 文件頁數： | 1/5頁 |
| 文件大?。?/td> | 112K |
| 代理商： | WED8L24514V |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED8L24514V
May 2000 Rev. 1
ECO #12800
FIG. 1
PIN NAMES
BLOCK DIAGRAM
PIN SYMBOLS
PIN CONFIGURATION
Asynchronous SRAM, 3.3V, 512Kx24
FEATURES
512Kx24 bit CMOS Static
Random Access Memory Array
Fast Access Times: 10, 12, and 15ns
Master Output Enable and Write Control
Three Chip Enables for Byte Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
119 Lead BGA (JEDEC MO-163), No. 391
Small Footprint, 14mmx22mm
Multiple Ground Pins for Maximum Noise Immunity
Single +3.3V (
±
5%) Supply Operation
DSP Memory Solution
Motorola DSP5630x
Analog Devices SHARC
TM
DESCRIPTION
The WED8L24514VxxBC is a 3.3V, twelve megabit SRAM con-
structed with three 512Kx8 die mounted on a multi-layer laminate
substrate. With 10 to 15ns access times, x24 width and a 3.3V
operating voltage, the WED8L24514V is ideal for creating a single chip
memory solution for the Motorola DSP5630x or a two chip solution
for the Analog Devices SHARC
TM
DSP.
The single or dual chip memory solutions offer improved system
performance by reducing the length of board traces and the number
of board connections compared to using multiple monolithic devices.
The JEDEC Standard 119 lead BGA provides a 61% space savings
over using three 512Kx8, 400 mil wide SOJs and the BGA package
has a maximum height of 110 mils compared to 148 mils for the SOJ
packages.
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/012
I/013
I/014
I/015
I/016
I/017
NC
I/018
I/019
I/020
I/021
I/022
I/023
NC
NC
AO
A5
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
A18
A9
A13
A1
A6
E2
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A10
A14
A2
E0
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
W
G
A3
A7
E3
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A11
A15
A4
A8
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
A17
A12
A16
NC
NC
I/00
I/01
I/02
I/03
I/04
I/05
NC
I/06
I/07
I/08
I/09
I/010
I/011
NC
NC
A
0-18
Address Inputs
E
Chip Enable
W
Master Write Enable
G
Master Output Enable
DQ
0-23
Common Data Input/Output
Power (3.3V
±
5%)
VCC
GND
Ground
NC
No Connection
512K x 24
Memory
Array
19
A
0
-A
18
G
W
E
0
E
2
E
3
DQ
0
-
7
DQ
8-15
DQ
16-23
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