- 您現在的位置：買賣IC網 > PDF目錄21989 > XC2S100-5TQG144C (Xilinx Inc)IC SPARTAN-II FPGA 100K 144-TQFP PDF資料下載
參數資料
| 型號： | XC2S100-5TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 49/99頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 100K 144-TQFP |
| 標準包裝： | 60 |
| 系列： | Spartan®-II |
| LAB/CLB數： | 600 |
| 邏輯元件/單元數： | 2700 |
| RAM 位總計： | 40960 |
| 輸入/輸出數： | 92 |
| 門數： | 100000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 產品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1305 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
53
R
Power-On Requirements
Spartan-II FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can
consume more than ICCPO minimum, though this cannot
adversely affect reliability.
A maximum limit for ICCPO is not specified. Therefore the
use of foldback/crowbar supplies and fuses deserves
special attention. In these cases, limit the ICCPO current to a
level below the trip point for over-current protection in order
to avoid inadvertently shutting down the supply.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol
Description
Conditions
New
Requirements(1)
For Devices with
Date Code 0321
or Later
Old
Requirements(1)
For Devices with
Date Code
before 0321
Units
Junction
Temperature(2)
Device
Temperature
Grade
Min
Max
Min
Max
I CCPO(3)
Total VCCINT supply
current required
during power-on
–40°C
≤ TJ<–20°C
Industrial
1.50
-
2.00
-
A
–20°C
≤ TJ < 0°C
Industrial
1.00
-
2.00
-
A
0°C
≤ TJ ≤ 85°C
Commercial
0.25
-
0.50
-
A
85°C < TJ ≤ 100°C
Industrial
0.50
-
0.50
-
A
TCCPO(4,5) VCCINT ramp time
–40°C
≤ TJ≤ 100°C
All
-
50
-
50
ms
Notes:
1.
The date code is printed on the top of the device’s package. See the "Device Part Marking" section in Module 1.
2.
The expected TJ range for the design determines the ICCPO minimum requirement. Use the applicable ranges in the junction
temperature column to find the associated current values in the appropriate new or old requirements column according to the date
code. Then choose the highest of these current values to serve as the minimum ICCPO requirement that must be met. For example,
if the junction temperature for a given design is -25°C
≤ TJ ≤ 75°C, then the new minimum ICCPO requirement is 1.5A.
If 5°C
≤ TJ ≤ 90°C, then the new minimum ICCPO requirement is 0.5A.
3.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 2.5V.
4.
The ramp time is measured from GND to VCCINT max on a fully loaded board.
5.
During power-on, the VCCINT ramp must increase steadily in voltage with no dips.
6.
For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL(1)
–0.5
0.8
2.0
5.5
0.4
2.4
24
–24
LVCMOS2
–0.5
0.7
1.7
5.5
0.4
1.9
12
–12
PCI, 3.3V
–0.5
44% VCCINT
60% VCCINT
VCCO + 0.5
10% VCCO
90% VCCO
Note (2)
PCI, 5.0V
–0.5
0.8
2.0
5.5
0.55
2.4
Note (2)
GTL
–0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
N/A
40
N/A
GTL+
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
N/A
36
N/A
HSTL I
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
7.6
–7.6
SSTL2 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
15.2
–15.2
相關PDF資料 |
PDF描述 |
|---|---|
| TACR476M003H | CAP TANT 47UF 3V 20% 0805 |
| XC3S400A-4FTG256C | IC SPARTAN-3A FPGA 400K 256FTBGA |
| XC3S200AN-4FTG256C | IC SPARTAN-3AN FPGA 200K 256FTBG |
| TACR476M002R | CAP TANT 47UF 2V 20% 0805 |
| RMC44DRYI | CONN EDGECARD 88POS DIP .100 SLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S100-5TQG144I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 100K GATES 2700 CELLS 263MHZ 2.5V 144TQFP EP - Trays 制造商:Xilinx 功能描述:XLXXC2S100-5TQG144I IC SYSTEM GATE |
| XC2S100-5VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S100-5VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S100-5VQG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S100-5VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
發(fā)布緊急采購，3分鐘左右您將得到回復。