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參數資料
| 型號： | XC2S30-5VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 24/99頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V 216 CLB'S 100-VQFP |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數： | 216 |
| 邏輯元件/單元數： | 972 |
| RAM 位總計： | 24576 |
| 輸入/輸出數： | 60 |
| 門數： | 30000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-VQFP（14x14） |
| 產品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1513-5 |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
30
R
Startup Delay Property
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the Startup
Sequence following device configuration is paused at a
user-specified point until the DLL locks. XAPP176:
Configuration and Readback of the Spartan-II and
Spartan-IIE Families explains how this can result in delaying
the assertion of the DONE pin until the DLL locks.
DLL Location Constraints
The DLLs are distributed such that there is one DLL in each
corner of the device. The location constraint LOC, attached
to the DLL primitive with the numeric identifier 0, 1, 2, or 3,
controls DLL location. The orientation of the four DLLs and
their corresponding clock resources appears in Figure 27.
The LOC property uses the following form.
LOC = DLL2
Design Considerations
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Input Clock
The output clock signal of a DLL, essentially a delayed
version of the input clock signal, reflects any instability on
the input clock in the output waveform. For this reason the
quality of the DLL input clock relates directly to the quality of
the output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the "DLL Timing
Parameters" section of the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially
available quartz crystal oscillator. For example, most crystal
oscillators produce an output waveform with a frequency
tolerance of 100 PPM, meaning 0.01 percent change in the
clock period. The DLL operates reliably on an input
waveform with a frequency drift of up to 1 ns — orders of
magnitude in excess of that needed to support any crystal
oscillator in the industry. However, the cycle-to-cycle jitter
must be kept to less than 300 ps in the low frequencies and
150 ps for the high frequencies.
Input Clock Changes
Changing the period of the input clock beyond the
maximum drift amount requires a manual reset of the
CLKDLL. Failure to reset the DLL will produce an unreliable
lock signal and output clock.
It is possible to stop the input clock in a way that has little
impact to the DLL. Stopping the clock should be limited to
less than approximately 100
μs to keep device cooling to a
minimum and maintain the validity of the current tap setting.
The clock should be stopped during a Low phase, and when
restored the full High period should be seen. During this
time LOCKED will stay High and remain High when the
clock is restored. If these conditions may not be met in the
design, apply a manual reset to the DLL after re-starting the
input clock, even if the LOCKED signal has not changed.
When the clock is stopped, one to four more clocks will still
be observed as the delay line is flushed. When the clock is
restarted, the output clocks will not be observed for one to
four clocks as the delay line is filled. The most common
case will be two or three clocks.
In a similar manner, a phase shift of the input clock is also
possible. The phase shift will propagate to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.
Output Clocks
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or route directly to destination clock
pins. The only BUFGs that the DLL clock outputs can drive
are the two on the same edge of the device (top or bottom).
One DLL output can drive more than one OBUF; however,
this adds skew.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Figure 27: Orientation of DLLs
DS001_27_061308
GCLKBUF1
DLL1
GCLKPAD1
GCLKBUF0
DLL0
GCLKPAD0
GCLKPAD2
DLL2
GCLKBUF2
GCLKPAD3
DLL3
GCLKBUF3
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S30-5VQG100I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S30-6CS144C | 功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC2S30-6CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S30-6CSG144C | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 144CSBGA - Trays |
| XC2S30-6CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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