- 您現在的位置：買賣IC網 > PDF目錄21991 > XC2S30-5VQG100C (Xilinx Inc)IC FPGA 2.5V 216 CLB'S 100-VQFP PDF資料下載
參數資料
| 型號： | XC2S30-5VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 30/99頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V 216 CLB'S 100-VQFP |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數： | 216 |
| 邏輯元件/單元數： | 972 |
| RAM 位總計： | 24576 |
| 輸入/輸出數： | 60 |
| 門數： | 30000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-VQFP（14x14） |
| 產品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1513-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
36
R
At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x7E is invalid.
At the fourth rising edge of CLKA, a read operation is
performed at memory location 0x0F and invalid data is
present on the DOA bus. Port B also executes a read
operation to memory location 0x0F and also reads invalid
data.
At the fifth rising edge of CLKA a read operation is
performed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Initialization
The block RAM memory can initialize during the device
configuration sequence. The 16 initialization properties of
64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 14. Any
initialization properties not explicitly set configure as zeros.
Partial initialization strings pad with zeros. Initialization
strings greater than 64 hex values generate an error. The
RAMs can be simulated with the initialization values using
generics in VHDL simulators and parameters in Verilog
simulators.
Initialization in VHDL
The block RAM structures may be initialized in VHDL for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization.
Initialization in Verilog
The block RAM structures may be initialized in Verilog for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a
defparam to pass the initialization.
Block Memory Generation
The CORE Generator software generates memory
structures using the block RAM features. This program
outputs VHDL or Verilog simulation code templates and an
EDIF file for inclusion in a design.
For design examples and more information on using the
Block RAM, see XAPP173, Using Block SelectRAM+
Memory in Spartan-II FPGAs.
Using Versatile I/O
The Spartan-II FPGA family includes a highly configurable,
high-performance I/O resource called Versatile I/O to
provide support for a wide variety of I/O standards. The
Versatile I/O resource is a robust set of features including
programmable control of output drive strength, slew rate,
and input delay and hold time. Taking advantage of the
flexibility and Versatile I/O features and the design
considerations described in this document can improve and
simplify system level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for
high-performance I/O becomes more important. While
chip-to-chip delays have an increasingly substantial impact
on overall system speed, the task of achieving the desired
system performance becomes more difficult with the
proliferation of low-voltage I/O standards. Versatile I/O, the
revolutionary input/output resources of Spartan-II devices,
has resolved this potential problem by providing a highly
configurable, high-performance alternative to the I/O
resources of more conventional programmable devices.
The Spartan-II FPGA Versatile I/O features combine the
flexibility and time-to-market advantages of programmable
logic with the high performance previously available only
with ASICs and custom ICs.
Each Versatile I/O block can support up to 16 I/O standards.
Supporting such a variety of I/O standards allows the
Table 14: RAM Initialization Properties
Property
Memory Cells
INIT_00
255 to 0
INIT_01
511 to 256
INIT_02
767 to 512
INIT_03
1023 to 768
INIT_04
1279 to 1024
INIT_05
1535 to 1280
INIT_06
1791 to 1536
INIT_07
2047 to 1792
INIT_08
2303 to 2048
INIT_09
2559 to 2304
INIT_0a
2815 to 2560
INIT_0b
3071 to 2816
INIT_0c
3327 to 3072
INIT_0d
3583 to 3328
INIT_0e
3839 to 3584
INIT_0f
4095 to 3840
Table 14: RAM Initialization Properties
Property
Memory Cells
相關PDF資料 |
PDF描述 |
|---|---|
| VI-27L-CW-F2 | CONVERTER MOD DC/DC 28V 100W |
| XC3S50AN-4TQG144C | IC SPARTAN-3AN FPGA 50K 144TQFP |
| XC3S50A-4FTG256C | IC SPARTAN-3A FPGA 50K 256FTBGA |
| VI-B5D-CX | CONVERTER MOD DC/DC 85V 75W |
| VI-27K-CW-F4 | CONVERTER MOD DC/DC 40V 100W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2S30-5VQG100I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S30-6CS144C | 功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC2S30-6CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S30-6CSG144C | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 144CSBGA - Trays |
| XC2S30-6CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
發布緊急采購，3分鐘左右您將得到回復。