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參數資料
| 型號： | 419UZ |
| 廠商： | Intersil Corporation |
| 元件分類： | 數字電位計 |
| 英文描述： | Single Digitally Controlled Potentiometer(XDCP) Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only |
| 中文描述： | 單數控電位（數字電位器）低噪聲，低功耗，SPI總線，128抽頭，雨刷只 |
| 文件頁數： | 13/13頁 |
| 文件大?。?/td> | 359K |
| 代理商： | 419UZ |
9
FN6311.0
June 28, 2006
Pin Description
Potentiometer Pins
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition and shorts RW to GND. When SHDN is returned to
logic high, the previous latch settings put RW at the same
resistance setting prior to shutdown. This pin is logically
OR’d with SHDN bit in ACR register. SPI interface is still
available in shutdown mode and all registers are accessible.
This pin must remain HIGH for normal operation.
Bus Interface Pins
Serial Clock (SCK)
This is the serial clock input of the SPI serial interface.
Serial Data Output (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
Serial Data Input (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Chip Select (CS)
CS LOW enables the ISL22419, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22419 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22419 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer and internally connected to VCC and GND.
The RW pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the
DCP is controlled by an 7-bit volatile Wiper Register (WR).
When the WR of a DCP contains all zeroes (WR[6:0]: 00h),
its wiper terminal (RW) is closest to GND. When the WR
register of a DCP contains all ones (WR[6:0]: 7Fh), its wiper
terminal (RW) is closest to VCC. As the value of the WR
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to GND
to the closest to VCC.
While the ISL22419 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between GND and VCC. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a non-
volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The ISL22419 contains one non-volatile 7-bit register, known
as the Initial Value Register (IVR), volatile 7-bit Wiper
Register (WR), and volatile 8-bit Access Control Register
(ACR). The memory map of ISL22419 is on Table 1. The
non-volatile register (IVR) at address 0, contains initial wiper
position and volatile register (WR) contains current wiper
position.
RW
FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2—
ACR
1Reserved
0IVR
WR
ISL22419
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