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參數資料
| 型號： | 419UZ |
| 廠商： | Intersil Corporation |
| 元件分類： | 數字電位計 |
| 英文描述： | Single Digitally Controlled Potentiometer(XDCP) Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only |
| 中文描述： | 單數控電位（數字電位器）低噪聲，低功耗，SPI總線，128抽頭，雨刷只 |
| 文件頁數： | 2/13頁 |
| 文件大小： | 359K |
| 代理商： | 419UZ |
10
FN6311.0
June 28, 2006
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically OR’d with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the WR
or ACR while WIP bit is 1.
SPI Serial Interface
The ISL22419 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22419. SCK and CS lines are
controlled by the host or master. The ISL22419 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22419 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
TABLE 3. IDENTIFICATION BYTE FORMAT
The next byte sent to the ISL22419 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
There are only two registers address possible for this DCP. If
the R1, R0 bits are zero, then the read or write is to either
the IVR or the WR register (depends of VOL bit at ACR). If
the R1 bit is 1and R0 bit is 0, then the operation is on the
ACR.
Write Operation
A Write operation to the ISL22419 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by Data Byte is sent to SDI pin. The host terminates the write
operation by pulling the CS pin from LOW to HIGH. For a
write to address 0 (WR), the byte at address 2 (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 12.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms.
Read Operation
A read operation to the ISL22419 is a three byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte followed
by “dummy” Data Byte is sent to SDI pin. The SPI host reads
the data from SDO pin on falling edge of SCK. The host
terminates the read operation by pulling the CS pin from
LOW to HIGH (see Figure 13).
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
76
5
432
1
0
BIT
NAME
VOL
SHDN
WIP
000
0
01010000
(MSB)
(LSB)
76543210
I3
I2
I1
I0
0
R1
R0
ISL22419
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