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參數資料
| 型號： | 48SD3208RPFK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | CAP 1.5UF 50V CERAMIC MONO 20% |
| 中文描述： | 32M X 8 SYNCHRONOUS DRAM, 6 ns, PDFP72 |
| 封裝： | DFP-72 |
| 文件頁數： | 7/39頁 |
| 文件大小： | 589K |
| 代理商： | 48SD3208RPFK |
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48SD3208
M
em
o
ry
15
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (8-Meg X 8-Bit X 4-Banks) SDRAM
01.10.05 Rev 2
To [ACTV]: This command makes the other bank active. ( However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of t
RAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the operation is completed.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM then enters precharge mode.
To [ACTV]: This command makes other banks active. (However, an interval of t
RRD is required.) Attempting
to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active result in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP]: After an auto-refresh cycle (after t
RC) the SDRAM automatically enters the IDLE state.
相關PDF資料 |
PDF描述 |
|---|---|
| 48SD3208RPFE | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFH | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFI | CAP 1.5UF 50V CERAMIC MONO 20% |
| 48SD3208 | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD6404RPFE | CAP 1200PF 100V CERAMIC MONO 5% |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 48SD6404 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
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