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參數(shù)資料
| 型號(hào)： | 61LV25616AL |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 256K × 16高速異步的CMOS靜態(tài)RAM為3.3V電源 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 67K |
| 代理商： | 61LV25616AL |
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
02/21/03
IS61LV25616AL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 3
(
WE
Controlled.
OE
is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 4
(
LB
,
UB
Controlled, Back-to-Back Write)
(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of
CE
= LOW,
UB
and/or
LB
= LOW, and
WE
= LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The
t
SA
,
t
HA
,
t
SD
, and
t
HD
timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with
OE
HIGH for a minimum of 4 ns before
WE
= LOW to place the I/O in a HIGH-Z state.
3.
WE
may be held LOW across many address cycles and the
LB
,
UB
pins can be used to control the Write function.
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