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參數(shù)資料
| 型號(hào)： | 61LV25616AL |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 256K × 16高速異步的CMOS靜態(tài)RAM為3.3V電源 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 67K |
| 代理商： | 61LV25616AL |
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
02/21/03
IS61LV25616AL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10
-12
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Parameter
Min. Max.
Min. Max.
Unit
Write Cycle Time
CE
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB
,
UB
Valid to End of Write
WE
Pulse Width
WE
Pulse Width (
OE
= LOW)
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
10
8
8
0
0
8
8
10
6
0
—
2
—
—
—
—
—
—
—
—
—
—
5
—
12
8
8
0
0
8
8
12
6
0
—
2
—
—
—
—
—
—
—
—
—
—
6
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
and
WE
LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the write.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
t
RC
t
PD
I
SB
I
CC
50%
V
DD
Supply
Current
50%
t
PU
READ CYCLE NO. 2
(1,3)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
,
UB
, or
LB
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transition.
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