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參數資料
| 型號： | 7005 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | ACT7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem |
| 中文描述： | ACT7005/7006單一封裝解決方案雙收發器，協議，子系統 |
| 文件頁數： | 16/29頁 |
| 文件大小： | 452K |
| 代理商： | 7005 |
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Aeroflex Circuit Technology
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
16
Operation
Function
RESET
RESET INPUT/OUTPUT BUFFERS
This command clears both the input and output FIFO buffers. The BUFF EF
flag will go low indicating the output buffer is empty.
READ OUTPUT
DATA BUFFER
READ OUTPUT FIFO
READS the data moved from the INTERNAL RAM in response to an
UNLOAD execute operation. The order of the data words corresponds to the
same order that they would be received on the 1553B bus. That is the first
data word read is the first data word following the COMMAND word. In the 8
bit mode the HIGH BYTE is read FIRST.
WRITE OUTPUT
DATA BUFFER
WRITE INPUT FIFO
WRITES the data that will be moved into the INTERNAL RAM in response to
a LOAD execute operation. The order of the data words corresponds to the
same order that they would be transmitted on the 1553B bus. That is the first
data word written is the first data word transmitted following the status word. In
8 bit mode the HIGH BYTE is written FIRST.
EXECUTE OP
EXECUTES OPERATION SPECIFIED IN OPERATION REGISTER
1. I/O BIT HIGH
Data currently in INPUT FIFO BUFFER is loaded into the INTERNAL
RAM block specified by the T/R BIT and SUBADDRESS FIELD of the
OPERATION REGISTER. The INPUT BUFFER must have at least one
data word. The DONE interrupt is pulsed when the operation is
completed.
2. I/O BIT LOW
An entire block of data (32 words) specified by the T/R and the
SUBADDRESS field of the OPERATION REGISTER is unloaded from
the INTERNAL RAM into the OUTPUT FIFO BUFFER. The BUFF EF
Flag goes high when the first data word is moved into the OUTPUT
BUFFER. The DONE interrupt is pulsed when the complete message
has been moved.
EXECUTE OP
WITH RPT OPTION
EXECUTES OPERATION SPECIFIED IN OPERATION REGISTER WITH
REPEAT OPTION
1. I/O BIT HIGH
Data previously written into the INPUT BUFFER is loaded into a new
INTERNAL RAM block specified by the T/R and SUBADDRESS field of
the OPERATION REGISTER. This operation allows a block of data
loaded in the INPUT BUFFER to be repeatedly copied into multiple
subaddresses of the INTERNAL RAM without the subsystem having to
reload the data. The DONE interrupt is pulsed when the operation is
completed. The intent of the operation is to minimize the time required to
initialize the INTERNAL RAM.
2. I/O BIT LOW
Operation identical to EXECUTE OP. WITHOUT RPT option.
TRIGGER TRANSACTION
TRIGGER TEST
TRANSACTION/TEST TRIGGER
This signal executes the desired Bus Controller Function or test of the
protocol section determined by the Operation Register.
Table 8 – Non-Register Operational Commands
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