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參數資料
型號: 7005
廠商: Aeroflex Inc.
英文描述: ACT7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem
中文描述: ACT7005/7006單一封裝解決方案雙收發器,協議,子系統
文件頁數: 7/29頁
文件大小: 452K
代理商: 7005
Aeroflex Circuit Technology
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
7
+5V
+5V
79
78
77
76
75
74
73
72
11
12
13
14
15
16
17
18
71
70
69
68
67
66
65
64
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
D15
D14 (MSB)
D13
D12
D11
D10
D9
D8
B8
B7
B6
B5
B4
B3
B2
B1
A
B
A8
A7
A6
A5
A4
A3
A2
A1
EN
D15
D14
D13
D12
D11
D10
D9
D8
9
8
7
6
5
4
3
2
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
B8
B7
B6
B5
B4
B3
B2
B1
A
B
A8
A7
A6
A5
A4
A3
A2
A1
EN
D7
D6
D5
D4
D3
D2
D1
D0
DS
RD
WR
A3
A2
A1
A0
INT *1
INT *2
DONE
SELF TEST
90
88
89
84
83
82
81
62
63
60
54
A3 (MSB)
A2
A1
A0 (LSB)
DS (Device Select)
RD (Read from RT/BC)
WR (Write to RT/BC)
GOOD BLOCK(RT)/VALID(BC)
VALID TRANS(RT)/INVALID(BC)
DONE
SELF-TEST
These are the recommended
interrupts, but use of them is
optional. The user can select any
combination of interrupts
depending on the needs of the
RT/BC. In addition to the 4
interrupts above, the user can
select from among 8 others to suit
the RT/BC needs.
+5V
R5
10K
85
28
31
1
86
AD10 OUT
AD10 IN
M 16/8
RESET
CLOCK
Master Reset
6MHz Clock
17
15
13
11
8
6
4
2
3
5
7
9
12
14
16
18
2G
1G
19
1
5 Bit RT Address and
Parity Bit. These lines
can be hardwired for an
RT address or they can
be set by jumpers, DIP
switches, or
TTL/CMOS latches.
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
R
R
R
R
R
R
2
80
50
48
47
41
43
44
OUTPUT GND
ANALOG GND
DIGITAL GND
LOGIC
OUTPUT GND
ANALOG GND
DIGITAL GND
TRANSCEIVER A
TRANSCEIVER B
TRANSFORMER-COUPLED
CONFIGURATION (LONG-STUB)
RT
Zo, 2%
R4, 2%
0.75Z
O
RT Z
O
2%
1
2
3
5
6
7
8
4
5
6
7
8
4
1
2
3
49
51
5
6
7
8
4
1
2
3
42
40
R3, 2%
0.75Z
O
R2
0.75Z
O
,2%
R1
0.75Z
O
,2%
DATA
DATA
DATA
DATA
DIRECT-COUPLED CONFIGURATION
(SHORT-STUB)
1553 DATA BUS
+
+
V
C
X
V
C
L
38
53
87
16
ACT7005/7006
N=1:2.5
N=1.4:1
U1
54LS245
U2
54LS245
U3
54LS244
Figure 3 – Typical Interface Connections
GND
GND
N=1:1.79
43
50
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