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參數資料
型號: 71M6543G-IGT/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP100
封裝: LEAD FREE, LQFP-100
文件頁數: 75/157頁
文件大小: 2178K
代理商: 71M6543G-IGT/F
71M6543F/H Data Sheet
8
24
2008-2010 MAXIM/TERIDIAN Semiconductor Corporation
v1.2
Table 6: I/O RAM Control Bits for Isolated Sensor
Name
Address
RST
Default
WAKE
Default
R/W Description
RCMD[4:0]
SFR
FC[4:0]
0
R/W
When the MPU writes a non-zero value to RCMD,
the 71M6543 issues a command to the cor-
responding isolated sensor selected with
RCMD[1:0]. When the command is complete, the
71M6543 clears RCMD[4:2]. The command code
itself is in RCMD[4:2].
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
R/W
The 71M6543 sets these bits to indicate that a
parity error on the isolated sensor has been de-
tected. Once set, the bits are remembered until
they are cleared by the MPU.
CHOPR[1:0]
2709[7:6]
00
R/W
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer frame.
01 – Positive
10 – Negative
11 – Same as 00
TMUXR2[2:0]
270A[2:0]
000
R/W The TMUX bits for control of the isolated sensor.
TMUXR4[2:0]
270A[6:4]
000
R/W The TMUX bits for control of the isolated sensor.
TMUXR6[2:0]
2709[2:0]
000
R/W The TMUX bits for control of the isolated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0
R
The read buffer for 71M6xx3 read operations.
RFLY_DIS
210C[3]
0
R/W
Controls how the 71M6543 drives the 71M6xx3
power pulse. When set, the power pulse is driven
high and low. When cleared, it is driven high
followed by an open circuit fly-back interval.
RMT2_E
2709[3]
0
R/W
Enables the isolated remote sensor interface and
re-configures pins IADC2-IADC3 as a balanced
pair digital remote interface.
RMT4_E
2709[4]
0
R/W
Enables the isolated remote sensor interface and
re-configures pins IADC4-IADC5 as a balanced
pair digital remote interface.
RMT6_E
2709[5]
0
R/W
Enables the isolated remote sensor interface and
re-configures pins IADC6-IADC7 as a balanced
pair digital remote interface.
Refer to Table 71 starting on page 104 for more complete details about these I/O RAM locations.
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