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參數(shù)資料
型號： 71M6543G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 9/157頁
文件大小： 2178K
代理商： 71M6543G-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
106
2008–2011 Teridian Semiconductor Corporation
v1.2
Name
Location Rst Wk Dir
Description
DIO_EEX[1:0]
2456[7:6]
0
–
R/W
When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM.
SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if
LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0]
Function
00
Disable EEPROM interface
01
2-Wire EEPROM interface
10
3-Wire EEPROM interface
11
3-Wire EEPROM interface with separate DO (SEGDIO3) and DI
(SEGDIO8) pins.
DIO_PV
2457[6]
0
–
R/W
Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0.
DIO_PW
2457[7]
0
–
R/W
Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0.
DIO_PX
2458[7]
0
–
R/W
Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0.
DIO_PY
2458[6]
0
–
R/W
Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0.
EEDATA[7:0]
SFR 9E
0
R/W
Serial EEPROM interface data.
EECTRL[7:0]
SFR 9F
0
R/W
Serial EEPROM interface control.
Status
Bit
Name
Read/
Write
Reset
State
Polarity Description
7
ERROR
R
0
Positive 1 when an illegal command is received.
6
BUSY
R
0
Positive 1 when serial data bus is busy.
5
RX_ACK
R
1
Positive
1 indicates that the EEPROM sent an
ACK bit.
EQU[2:0]
2106[7:5]
0
R/W
Specifies the power equation.
EQU[2:0]
Description
Element
0
Element
1
Element
2
Recommended
MUX Sequence
3
2 element, 4W,
3
φ Del
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