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參數資料
型號: 71M6543GH-IGT/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP100
封裝: LEAD FREE, LQFP-100
文件頁數: 123/157頁
文件大小: 2178K
代理商: 71M6543GH-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
68
2008–2011 Teridian Semiconductor Corporation
v1.2
Figure 19: 3-wire Interface. Write Command, HiZ=1
Figure 20: 3-wire Interface. Read Command.
Figure 21: 3-Wire Interface. Write Command when CNT=0
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
2.5.12 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface
to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed
with the combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39 (pins 3, 2, 1 and 100).
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
CNT Cycles (6 shown)
Write -- With HiZ
INT5
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (output)
D2
D3
D4
D5
D6
D7
(HiZ)
(LoZ)
SDATA output Z
CNT Cycles (8 shown)
READ
D0
D1
D2
D3
D4
D5
INT5
D6
D7
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (input)
SDATA output Z
(HiZ)
CNT Cycles (0 shown)
Write -- No HiZ
D7
INT5 not issued
CNT Cycles (0 shown)
Write -- HiZ
INT5 not issued
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (output)
SCLK (output)
BUSY (bit)
SDATA (output)
(HiZ)
SDATA output Z
(LoZ)
CNT Cycles (6 shown)
Write -- With HiZ and WFR
EECTRL Byte Written
SCLK (output)
BUSY (bit)
SDATA (out/in)
D2
D3
D4
D5
D6
D7
BUSY
READY
(From EEPROM)
INT5
(From 6520)
SDATA output Z
(HiZ)
(LoZ)
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