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參數資料
| 型號： | 71M6543GH-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數： | 139/157頁 |
| 文件大小： | 2178K |
| 代理商： | 71M6543GH-IGT/F |
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71M6543F/H and 71M6543G/GH Data Sheet
82
2008–2011 Teridian Semiconductor Corporation
v1.2
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and
when ICE_E=1.
3.4
Wake-Up Behavior
As described above, the part always wakes up in MSN mode when system power is restored. As stated
in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated by a wake-
up timer timeout, when the pushbutton (PB) input is activated, a rising edge on SEGDIO4, SEGDIO52 or
SEGDIO55, or by activity on the RX or OPT_RX pins.
3.4.1
Wake on Hardware Events
The following pin signal events wake the 71M6543 from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin, or a high level on
the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 64 for de-bounce details on each pin and
for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52, and SEGDIO55 pins must
be configured as DIO inputs and their wake enable (EW_x bits) must be set. In SLP and LCD modes, the
MPU is held in reset and cannot poll pins or react to interrupts. When one of the hardware wake events
occurs, the internal WAKE signal rises and within three CK32 cycles the MPU begins to execute. The
MPU can determine which one of the pins awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4,
WF_DIO52, or WF_DIO55 flags (see Table 64).
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 64 shows which pins are equipped with de-bounce circuitry.
Pins that do not have de-bounce circuits must still be high for at least 2 s to be recognized.
The wake enable and flag bits are shown in Table 64. The wake flag bits are set by hardware when the
MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the part
is already awake. Table 66 lists the events that clear the WF flags.
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 64, each of these
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wakeup is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicates that
system power is stable.
Table 64: Wake Enable and Flag Bits
Wake Enable
Wake Flag
De-bounce
Description
Name
Location
Name
Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Timer.
EW_PB
28B3[3]
WF_PB
28B1[3]
Yes
Wake on PB.*
EW_RX
28B3[4]
WF_RX
28B1[4]
2 s
Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 s
Wake on SEGDIO4.
EW_DIO52
28B3[1]
WF_DIO52
28B1[1]
Yes
Wake on SEGDIO52.*
EW_DIO55
28B3[0]
WF_DIO55
28B1[0]
Yes
OPT_RXDIS = 1: Wake on DIO55 with
64 ms de-bounce.*
OPT_RXDIS = 0: Wake on either edge
of OPT_RX with 2 s de-bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Always Enabled
WF_RST
28B0[6]
2 s
Wake after RESET.
Always Enabled
WF_RSTBIT
28B0[5]
No
Wake after RESET bit.
Always Enabled
WF_ERST
28B0[3]
2 s
Wake after E_RST.
(ICE must be enabled)
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