
TM1300 Data Book
Philips Semiconductors
A-130
PRODUCT SPECIFICATION
32-bit load with index
SYNTAX
[ IF r
guard ] ld32r rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs
← 3
else
bs
← 0
r
dest<7:0>
← mem[rsrc1 + rsrc2 + (3 ⊕ bs)]
r
dest<15:8>
← mem[rsrc1 + rsrc2 + (2 ⊕ bs)]
r
dest<23:16>
← mem[rsrc1 + rsrc2 + (1 ⊕ bs)]
r
dest<31:24>
← mem[rsrc1 + rsrc2 + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit
dmem
Operation code
200
Number of operands
2
Modier
No
Modier range
—
Latency
3
Issue slots
4, 5
DESCRIPTION
The ld32r operation loads the 32-bit memory value from the address computed by r
src1 +rsrc2 and stores the
result in r
dest. If the memory address computed by rsrc1 +rsrc2 is not a multiple of 4, the result of ld32r is
undened but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
The ld32r operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
memory operations is undened). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32r.
The ld32r operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register and the occurrence of side effects. If the LSB of r
guard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of r
guard is 0, rdest is not
changed and ld32r has no side effects whatever.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xcfc, r20 = 0x4,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
ld32r r10 r20
→ r80
r80
← 0x84332211
r50 = 0, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r50 ld32r r40 r30
→ r90
no change, since guard is false
r60 = 1, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
IF r60 ld32r r40 r30
→ r100
r100
← 0x48665544
r50 = 0xd01, r30 = 0xfffffff8
ld32r r70 r30
→ r110
r110 undened, since 0xd01 +(–8) is not a
multiple of 2
SEE ALSO
ld32 ld32d ld32x st32
st32d h_st32d
ld32r