
AB
C
H
E
D
F
G
I
J
K
LM N
O
P
Q
RS
T
U
V W X
Y
Z
PRODUCT SPECIFICATION
Index-9
IPENDING
picture 3-11
IS 11172-2 references 15-3
IS 13818-2 references
table 15-3
ISETTING0
picture 3-10
ISETTING1
picture 3-10
ISETTING2
picture 3-10
ISETTING3
picture 3-10
isub A-122
isubi A-123
izero A-124
J
jmpf A-125
jmpi A-126
jmpt A-127
JTAG
additional registers
picture 18-4
BYPASS instruction 18-2
communication protocol 18-5
example datat transfer 18-5
EXTEST instruction 18-2
instruction encodings
table 18-2
instructions
SEL_DATA_IN 18-5
SEL_DATA_OUT 18-5
SEL_IFULL_IN 18-5
SEL_JTAG_CTRL 18-5
SEL_OFULL_OUT 18-5
MACRO instruction 18-3
MMIO registers
table 18-4
overview 18-1
race condition,avoid 18-5
RESET instruction 18-2
SAMPLE/PRELOAD instruction 18-2
SEL_DATA_IN instruction 18-2
SEL_DATA_OUT instruction 18-2
SEL_IFULL_IN instruction 18-2
SEL_JTAG_CTRL instruction 18-2
SEL_OFULL_OUT instruction 18-2
system components 18-3
TAP controller description 18-1
TAP controller state diagram,picture 18-2
test access port 18-1
test clock 18-1, 18-3
test data in 18-1
test data out 18-1
test mode select 18-1
virtual registers 18-4
JTAG_CTRL
register 18-4
JTAG_DATA_IN
register 18-4
JTAG_DATA_OUT
register 18-4
JTAG_IFULL_IN 18-4
JTAG_OFULL_OUT 18-4
K
keying
chroma 14-9
color 14-9
L
latency timer
PCI interface register 11-7
latency,memory operation 5-8
ld32 A-128
ld32d A-129
ld32r A-130
ld32x A-131
level sensitive interrupts 3-10
lines
mirroring 14-15
load coefficients parameter table 14-22
load store ordering 3-5
locking conditions 5-4
locking range 5-4
LRU bit definition 5-12
LRU bit definitions,picture 5-12
LRU bit update ordering 5-12
LRU initialization 5-12
LRU replacement,cache 5-11
LRU, hierarchical 5-4
LRU,four-way 5-11
LRU,two-way 5-11
lsl A-132
lsli A-133
lsr A-134
lsri A-135
M
macro block header 15-1