
TM1300 Data Book
Philips Semiconductors
11-4
PRODUCT SPECIFICATION
I/O (I/O access enable). This bit controls a device’s abil-
ity to respond to I/O-space accesses. A value of ’0’ dis-
ables PCI device response; a value of ’1’enables re-
sponse. This bit is hardwired to ’0’ because all TM1300
internal registers are memory mapped.
MA (Memory access enable). This bit controls re-
sponse to memory-space accesses. A value of ’0’ dis-
ables TM1300 response; a value of ’1’ enables re-
sponse. This bit is set to ’0’ at power-up; software can set
this bit to ’1’ with a configuration write.
31
00
0
Normally ’0’
0
Hardwired to ground
sp
Set by software if aperture size allows
p
Set by software
1
Normally one
1
Hardwired to Vdd
s
Set by hardware from boot EEPROM
0
15
Device ID (0x5402)
Vendor ID (0x1131)
0
04
01
000
reserved
11
1
Status
Command
0000
0
0
08
10
100
010000010
Class Code (0x048000)
Revision ID (see text)
0000
0
000
0
000
00
0
0C
00
000
0
BIST (0x00)
Latency Timer
0000
0
000
0
ppp
p
00
p
Header Type (0x00)
Cache Line Size
p
10
sp sp
sp sp sp
0
DRAM Base Address
pppp
sp
000
0
000
00
0
00
0
p
14
pp
ppp
0
MMIO Base Address
pppp
p
0
000
0
000
00
0
00
0
18, 1C,
20, 24
28
30
34, 38
3C
000
1
Interrupt Line
0
011
0
000
00
0
p
2C
s
sss
ss
s
ss
s
p
Interrupt Pin (0x01)
Min_Gnt (0x03)
Max_Lat (0x01)
0000
001
0
7
23
01010100000000100001000100110001
00
p
00
0
Configuration-Space
Address
Offset
0
00
000
000000000
Four other base address registers
0000
0
000
0
000
00
0
00
000
0
0000
0
000
00
0
Reserved register
0
Expansion Rom Base Address
0
000
0
000
00
0
00
0
Two reserved registers
0
000
0
000
00
0
00
0
00000000
000
00
0
000
0000
0
000
0000
0
s
sss
ss
s
ss
s
Subsystem ID
Subsystem Vendor ID
00
p
0
Key
Figure 11-2. PCI configuration header region register layout and initial values. (All values in hex.)
15
0
Command Register
I/O
1
MA
2
EM
3
SC
4
MWI
5
VGA
6
PAR
7
Wait
8
SERR#
9
FB
10
Reserved
Figure 11-3. Command Register format.