
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-181
IEEE status ags from convert unsigned integer
to oating-point with rounding toward zero
SYNTAX
[ IF r
guard ] ufloatrzflags rsrc1
→ rdest
FUNCTION
if r
guard then
r
dest
← ieee_ags((oat) ((unsigned long)rsrc1))
ATTRIBUTES
Function unit
falu
Operation code
120
Number of operands
1
Modier
No
Modier range
—
Latency
3
Issue slots
1, 4
DESCRIPTION
The ufloatrzflags operation computes the IEEE exceptions that would result from converting the unsigned
integer in r
src1 to a single-precision IEEE oating-point value, and an integer bit vector representing the computed
exception ags is written into r
dest. The bit vector stored in rdest has the same format as the IEEE exception bits in
the PCSW. The exception ags in PCSW are left unchanged by this operation. Rounding is performed toward zero;
the IEEE rounding mode bits in PCSW are ignored.
The ufloatrzflags operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls
the modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 3
ufloatrzflags r30
→ r100
r100
← 0
r40 = 0xffffffff (4294967295)
ufloatrzflags r40
→ r105
r105
← 0x02 (INX)
r10 = 0, r50 = 0xfffffffd
IF r10 ufloatrzflags r50
→ r110
no change, since guard is false
r20 = 1, r50 = 0xfffffffd
IF r20 ufloatrzflags r50
→ r115
r115
← 0x02 (INX)
r60 = 0x7fffffff (2147483647)
ufloatrzflags r60
→ r117
r117
← 0x02 (INX)
r70 = 0x80000000 (2147483648)
ufloatrzflags r70
→ r120
r120
← 0
r80 = 0x7ffffff1 (2147483633)
ufloatrzflags r80
→ r122
r122
← 0x02 (INX)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
31
00
SEE ALSO
ufloatrz ifloatflags
ufloatflags ifloatrzflags
ufloatrzflags