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參數資料
| 型號： | 935269576557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, HEAT SINK, PLASTIC, SOT-638-1, TQFP-100 |
| 文件頁數： | 21/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269576557 |
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Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
28 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
6.1 Clocks Video Submodule
The generation of the various clock signals needed for video pipelines takes place in the clocks
video module. Figure 22 shows a block diagram of this module. The configuration registers for
the clocks module can be found in Section 10. Audio/Clock Address Space.
6.2 Clocks Audio Submodule
The input clocks for the audio block are generated in the clocks audio submodule. Figure 23
shows a block diagram for this submodule.
7.
Test Mode
This section describes how the analog test modes are implemented in the PNX8510/11. Note
that these test modes are intended for production test only. The chip needs to be brought into
analog test mode via the JTAG boundary scan controller. Once the chip is in analog test mode
the different test modes can be enabled via the GPIO pins. The data input for the video DAC’s is
provided via the DV1 interface for DACs 1 through 4 and via the DV2 interface for DACs 5 and 6
respectively. The “main switch” for the test mode is controlled by the JTAG boundary scan
controller. Once the chip is in analog test mode, the GPIO pins can be used to select certain
combinations outlined in the tables.
Figure 22: Clocks Video Submodule
clocks_sel
dv_clk
div by 1, 2, 3 or 4
dv_clk
div by 1, 2, 3 or 4
clock divider
&
degilitcher
clocks_sel
clock divider
&
degilitcher
dv_clk
sel_v
test
clk_dv_if_out
clk_dv_proc_out
Figure 23: Clocks Audio Submodule
4-bit divider
9-bit divider
i2s_aos_clk
sel_a
sck_in
ws_in
test_a
clk_a
sclk_a
ws_a
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