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參數(shù)資料
| 型號： | 935273871518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 10/61頁 |
| 文件大小： | 326K |
| 代理商： | 935273871518 |
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2004 May 18
18
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
The coast signal may be active either HIGH or LOW by
setting bit COS.
It is possible to control the phase of the ADC clock via the
I2C-bus with the included digital phase-shift controller. The
phase register (5 bits) enables to shift the phase by steps
of 11.25 deg.
The PLL also provides a CKDATA clock. This clock is
synchronized with the data outputs whatever the output
mode is.
It is possible to delay the CKDATA clock with a constant
delay (t = 2 ns compared to the outputs) by setting
bit CKDD = 1. Moreover, it is possible to invert this output
by setting bit CKDATINV = 1.
When the PLL reference signal comes from the separator,
the PLL rising edge must be preferably used in order to not
use the PLL coast mode. It should be noted that the
HSYNCO output of the sync separator is always a mostly
low signal, whatever is the polarity of the composite sync
input. The VSYNCO output signal of the sync separator is
also mostly low signal. It is at a high state during the
vertical blanking.
8.5
Sync-on-green
When the SOG input is selected (bit SOGSEL = 1), the
SOG charge pump current bits SOGI[1:0] should be
programmed in function of the input signal; see Table 1.
A hum remover is implemented in the SOG. It removes
completely the hum perturbation on the first or second
edge of the horizontal sync pulse for digital video input like
VESA, and on the second edge only for analog video input
signal like TV or HDTV.
The maximum hum perturbation is 250 mV (p-p) at 60 Hz
to have a correct SOG functionality.
Table 1
Charge pump current programming; note 1
Note
1. Definitions:
Tvideo = total time in 2 frames when video signal is strictly superior to black level.
Tline = total time of 2 frames.
Tsync = total time in 2 frames when the video signal is strictly inferior to black level.
BITS SOGI[1:0]
MAXIMUM VALUE
Tvideo / Tline
MAXIMUM VALUE
Tsync / Tline
STANDARD
00
83.5 %
14.8 %
TV standards and non-VESA standards
01
86.0 %
12.6 %
all TV, HDTV and VESA standards
10
90.5 %
8.6 %
HDTV standards or non-VESA standards
11
test mode
8.6
Programmable coast
When the values of PRECOAST[2:0] = 0 and
POSTCOAST[4:0] = 0, the coast pulse equals the Vsync
input.
When an interlaced signal is used, the regenerated coast
pulse width may vary from one frame to another of one
Hsync pulse. In that case, the programmed value of
PRECOAST[2:0] needs to be increased by one compared
to the expected minimum number of Hsync coast pulses
before the vertical sync signal.
8.7
Data enable
This signal qualifies the active data period on the
horizontal line. Pin DEO = HIGH during the active display
time and LOW during the blank time. The start of this
signal can be adjusted with bits HSYNCL[9:0] and
HBACKL[9:0]. The length of this signal can be adjusted
with bits HDISPL[11:0].
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