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參數(shù)資料
型號(hào)： 935273871518
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 13/61頁(yè)
文件大小： 326K
代理商： 935273871518
2004 May 18
20
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
Table 4
Write format bit description
9.1.2
WRITE ALL REGISTERS
All registers are programmed one after the other, by giving this initial condition (XX11 1111) as the subaddress state;
thus, the registers are charged following the predefined sequence of 32 bytes (from subaddress 0 0000 to 1 1111).
Table 5
I2C-bus sequence for writing all registers
Table 6
Byte format for writing all registers
BIT
SYMBOL
DESCRIPTION
Byte 1
7 to 1
A[6:0]
Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level
on pin A0.
0R/W
Write command bit. If R/W = 0, then write action.
Byte 2
7 to 6
not used
5
MODE
Mode selection bit. If MODE = 0, then each register can be written independently.
4 to 0
SA[4:0]
Register subaddress. Subaddress of the selected register (from 0 0000 to 1 1111).
Byte 3
7 to 0
D[7:0]
Data 1. This value is written in the selected register.
SDA LINE
DESCRIPTION
S
master starts with a start condition
Byte 1
master transmits device address (7 bits) plus write command bit (R/W=0)
A
slave generates an acknowledge
Byte 2
master transmits programming mode and subregister address to start writing to
A
slave generates an acknowledge
Byte 3
master transmits data 1
A
slave generates an acknowledge
::
Byte 34
master transmits data 32
A
slave generates an acknowledge
P
master generates a stop condition
BIT
76543210
Byte 1
device address
R/W
A6
A5
A4
A3
A2
A1
A0
100110
X
0
Byte 2
programming mode
register subaddress
MODE
SA4
SA3
SA2
SA1
SA0
X
111111
Byte (2 + n)
data n
D7
D6
D5
D4
D3
D2
D1
D0
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