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參數(shù)資料
| 型號： | 935273871518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 54/61頁 |
| 文件大小： | 326K |
| 代理商： | 935273871518 |
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TDA8754; Triple 8-bit video ADC up to 270 Msps
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Product description
TDA8754; Triple 8-bit video ADC up to 270 Msps + Stay informed
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General description
The TDA8754 is a complete triple 8-bit ADC with an integrated PLL running up to 270 Msps and analog preprocessing functions (clamp and PGA) optimized for capturing
RGB/YUV graphic signals.
The PLL generates a pixel clock from inputs HSYNC and COAST.
The TDA8754 offers full sync processing for sync-on-green applications. A clamp signal may be generated internally or provided externally.
The clamp levels, gains and other settings are controlled via the IC-bus interface.
This IC supports display resolutions up to QXGA (2048 X 1536) at 85 Hz.
Features
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3.3 V power supply
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Triple 8-bit ADC:
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0.25 LSB differential non-linearity (DNL)
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0.6 LSB integral non-linearity (INL).
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Analog sampling rate from 12 Msps up to 270 Msps
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Maximum data rate:
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Single port mode: 140 MHz
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Dual port mode: 270 MHz
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3.3 V LV-TTL outputs.
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PLL control via IC-bus:
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390 ps PLL jitter peak to peak at 270 MHz
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Low PLL drift with temperature (2 phase steps maximum)
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PLL generates the ADC sampling clock which can be locked on the line frequency from 15 kHz to 150 kHz
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Integrated PLL divider
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Programmable phase clock adjustment cells.
file:///C|/Documents%20and%20Settings/lakshmip/Local%20Settings/Temp/notesFEC990/TDA8754HL.htm (1 of 4) [1/28/2005 5:27:28 PM]
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