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參數(shù)資料
型號(hào)： A3PN125-2VQG100
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝： 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件頁(yè)數(shù)： 76/106頁(yè)
文件大小： 3324K
代理商： A3PN125-2VQG100
ProASIC3 nano Flash FPGAs
R e visio n 8
2 - 57
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-73 ProASIC3 nano CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks 1,2
200
ps
Number of Programmable Values in Each Programmable Delay
Block
32
Serial Clock (SCLK) for Dynamic PLL 3,4
125
MHz
Input Cycle-to-Cycle Jitter (peak magnitude)
1.5
ns
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 6
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay
1 1,2
1.25
15.65
ns
Delay Range in Block: Programmable Delay
2 1,2
0.025
15.65
ns
Delay Range in Block: Fixed Delay 1,2
2.2
ns
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
5
Max Peak-to-Peak Jitter Data 5,7,8
SSO
≤ 2
SSO
≤ 4
SSO
≤ 8SSO ≤ 16
0.75 MHz to 50MHz
0.50%
0.70%
1.00%
50 MHz to 250 MHz
1.00%
3.00%
5.00%
9.00%
250 MHz to 350 MHz
2.50%
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
4. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.
5. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI =
3.3 , VQ/PQ/TQ type of packages, 20 pF load.
8. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of
each other.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PN125-2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門(mén)數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-DIELOT 制造商:Microsemi Corporation 功能描述:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN125-VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門(mén)數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門(mén)數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-VQG100 功能描述:IC FPGA NANO 1024MAC 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門(mén)數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
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