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參數資料
型號: A40MX04-FPL44
元件分類: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC44
封裝: PLASTIC, LCC-44
文件頁數: 30/124頁
文件大小: 3142K
代理商: A40MX04-FPL44
40MX and 42MX FPGA Families
v6.1
1-7
Programming
Device programming is supported through the Silicon
Sculptor series of programmers. Silicon Sculptor II is a
compact,
robust,
single-site
and
multi-site
device
programmer for the PC. With standalone software,
Silicon Sculptor II is designed to allow concurrent
programming of multiple units from the same PC.
Silicon Sculptor II programs devices independently to
achieve the fastest programming times possible. After
being programmed, each fuse is verified to insure that it
has been programmed correctly. Furthermore, at the end
of programming, there are integrity tests that are run to
ensure no extra fuses have been programmed. Not only
does
it
test
fuses
(both
programmed
and
nonprogrammed), Silicon Sculptor II also allows self-test
to verify its own hardware extensively.
The procedure for programming an MX device using
Silicon Sculptor II is as follows:
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Actel
offers
device
volume-programming
services
either
through
distribution
partners
or
via
In-House
Programming from the factory.
For more details on programming MX devices, please
refer to the Programming Antifuse Devices and the
Silicon Sculptor II user's guides.
Power Supply
MX devices are designed to operate in both 5.0V and
3.3V environments. In particular, 42MX devices can
operate in mixed 5.0V/3.3V systems. Table 1 describes the
voltage support of MX devices.
Power-Up/Down in Mixed-Voltage Mode
When powering up 42MX in mixed voltage mode
(VCCA =5.0V and VCCI = 3.3V), VCCA must be greater than
or equal to VCCI throughout the power-up sequence. If
VCCI exceeds VCCA during power up, either the I/Os' input
protection junction on the I/Os will be forward-biased or
the I/Os will be at logical HIGH, and ICC rises to high
levels. For power-down, any sequence with VCCA and
VCCI can be implemented.
Low Power Mode
42MX devices have been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated. Since the core of the device is
turned off, the states of the registers are lost. The device
must be re-initialized when exiting Low Power Mode. I/
Os can be driven during LP mode, and clock pins should
be driven HIGH or LOW and should not float to avoid
drawing current. To exit LP mode, the LP pin must be
pulled LOW for over 200 s to allow for charge pumps to
power up, and device initialization will begin.
Figure 1-11 Fuselock
e
u
Table 1
Voltage Support of MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0V
5.5V
5.0V
3.3V
3.6V
3.3V
42MX
5.0V
5.5V
5.0V
3.3V
3.6V
3.3V
5.0V
3.3V
5.5V
3.3V
相關PDF資料
PDF描述
A40MX04-FPL68X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL68 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL84X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPL84 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPQ100X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100
相關代理商/技術參數
參數描述
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A40MX04-FPL68I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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