
REV. 0
–12–
AD7654
CIRCUIT INFORMATION
The AD7654 is a very fast, low power, single-supply, precise
simultaneous sampling 16-bit analog-to-digital converter (ADC).
The AD7654 provides the user with two on-chip track-and-hold,
successive approximation ADCs that do not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications. The AD7654 can be also used as a 4-channel ADC
with two pairs simultaneously sampled.
The AD7654 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in
48-lead LQFP or tiny 48-lead LFCSP packages that combine
space savings and allow flexible configurations as either a serial
or parallel interface. The AD7654 is pin-to-pin-compatible with
PulSAR ADCs.
Modes of Operation
The AD7654 features two modes of operation, Normal and
Impulse. Each of these modes is more suitable for specific
applications.
The Normal Mode is the fastest mode (500 kSPS). Except when it
is powered down (PD HIGH), the power dissipation is almost
independent of the sampling rate.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 444 kSPS. When operating at 10 kSPS, for
example, it typically consumes only 2.6 mW. This feature makes
the AD7654 ideal for battery-powered applications.
Transfer Functions
The AD7654 data format is straight binary. The ideal transfer
characteristic for the AD7654 is shown in Figure 3 and Table I.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS–1.5 LSB
+FS–1 LSB
–FS+1 LSB
–FS
–FS+0.5 LSB
A
Figure 3. ADC Ideal Transfer Function
Table I. Output Codes and Ideal Input Voltages
Analog
Input V
REF
= 2.5 V
4.999924 V
4.999847 V
2.500076 V
2.5 V
2.499924 V
–76.29
μ
V
0 V
Digital Output
Code (Hexa)
FFFF
1
FFFE
8001
8000
7FFF
0001
0000
2
Description
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
NOTES
1
This is also the code for overrange analog input (V
INx
– V
INxN
above 2
×
(V
REF
–
V
)).
2
This is also the code for underrange analog input (V
INx
below V
INxN
).
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7654.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
Figure 4 shows a simplified analog input section of the AD7654.
INAx
INBx
AGND
AVDD
C
S
C
S
R
B
= 500
R
A
= 500
Figure 4. Simplified Analog Input
The diodes shown in Figure 4 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input
signal never exceeds the absolute ratings on these inputs. This
will cause these diodes to become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 120 mA maximum. This condition could eventually
occur when the input buffer’s (U1) or (U2) supplies are different
from AVDD. In such case, an input buffer with a short-circuit
current limitation can be used to protect the part.
This analog input structure allows the sampling of the differential
signal between INx and INxN. Unlike other converters, the
INxN is sampled at the same time as the INx input. By using
these differential inputs, small signals common to both inputs
are rejected.