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參數資料
| 型號： | AD7654AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數： | 19/24頁 |
| 文件大小： | 734K |
| 代理商： | AD7654AST |
REV. 0
AD7654
–19–
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the results of this conversion can be read while both
CS
and
RD
are low. The data from both channels are shifted out,
MSB first, with 32 clock pulses, and is valid on both rising and
falling edge of the clock.
One advantage of this method is that the conversion perfor-
mance is not degraded because there are no voltage transients on
the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7654 provides a daisy-chain
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired, as it is for
instance, in isolated multiconverters applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the edge of SCLK opposite the one used to shift out
the data on SDOUT. Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
External Clock Data Read during Conversion
Figure 18 shows the detailed timing diagrams of this method.
During a conversion, while both
CS
and
RD
are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 32 clock pulses, and is valid on both rising and
falling edges of the clock. The 32 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain fea-
ture in this mode, and RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
CNVST
SDOUT
SCLK
X
CH A D15
1
2
3
31
32
t
3
t
42
t
43
t
44
t
38
t
39
t
23
BUSY
INVSCLK = 0
CS
EXT/
INT
= 1
CH B D0
CH B D1
CH A D13
CH A D14
RD
= 0
EOC
t
10
t
11
t
13
t
12
A/
B
= 1
Figure 18. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
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| AD7654ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7654ASTZ | 功能描述:IC ADC 16BIT 500KSPS DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7654ASTZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7654 LQFP48 |
| AD7654ASTZRL | 功能描述:IC ADC 16BIT DUAL 2CH 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
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